DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to submission of application on 31-DEC-2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 31-DEC-2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Server “105” found in Fig. 1B.
Data controller “888” found in Fig. 2B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-7, 9-13, 15-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1, 3-7, 9-12 (Statutory Category – Process)
Step 2A – Prong 1: Judicial Exception Recited?
Claim 1 recites
Selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command
The limitation of Selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, nothing in the claim element precludes the step from practically being performed in the mind. For example, “Selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command” in the context of this claim encompasses the user mentally observing the data units in the cache, and pointing one out to be the eviction candidate.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A – Prong 2: Integrated into a Practical Application?
This judicial exception is not integrated into a practical application.
Additionally, other elements recite receiving, by a storage device comprising a cache and nonvolatile memory, a command to place a lock on a first data unit stored in the cache. The receiving is insignificant extra-solution activity, as they recite a basic receipt of a known command at a high level of generality. The additional elements do not meaningfully limit how the mental process is performed or how it is used in a solution (see MPEP 2106.05(g)).
Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: Claim provides an Inventive Concept?
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
As discussed above with respect to Step 2A, the additional limitations are insignificant extra-solution activity and don’t impose any meaningful limits on practicing the abstract idea.
Further, in regards to Step 2B, the additional computer functions have been recognized to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (see MPEP 2106.05(d)(II)).
The additional element of receiving, by a storage device comprising a cache and nonvolatile memory, a command to place a lock on a first data unit stored in the cache covers well-understood, routine, and conventional functions of a basic receiving a known command, which is recited in a merely generic manner, and does not provide an inventive concept. One example of this command to place a lock on a data unit stored in the cache being known in the art is in [0022] and [0027] YAMAMURA et al., U.S. Pub. No. 20090172289, which describes the existence other methods and conventional arts of a programmer performing a locking operation on an area (cache line or cache way) of the cache.
The additional elements have been considered both individually and as an ordered combination in the significantly more consideration.
The claim is ineligible.
Claim 3 recites: “The method of claim 1, wherein the selecting of the second data unit for eviction comprises selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the command.” The limitation merely adds another condition to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 4 recites: “The method of claim 3, wherein the first data unit is excluded from the set of data units based on the command.” The limitation merely adds another condition to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 5 recites: “The method of claim 1, wherein: the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the command.” All of these limitations merely add additional conditions and results to the decision-making and are therefore considered part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 6 recites: “The method of claim 5, wherein the data unit characteristic is based on recency of usage”. The limitation adds an additional condition to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 7 recites: “The method of claim 5, wherein: the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being the highest-ranked data that is not locked.” These limitations add additional conditions and steps to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 9 recites: “The method of claim 1, further comprising: receiving a prefetch command for a third data unit; determining that the third data unit is absent from the cache; storing the prefetch command in a prefetch queue, the storing of the prefetch command in the prefetch queue being based on the determining that the third data unit is absent from the cache.” The receiving a prefetch command and storing the prefetch command in a prefetch queue are insignificant extra-solution activity at a high level of generality, and represents well-understood, routine, and conventional activity as shown in Grayson U.S. Pub. No. 20060136696, which teaches in [0015] that the usage of prefetch queues for storing prefetch requests of data have been known to one of ordinary skill in the art. Therefore, these limitations fail to integrate the judicial exceptions into a practical application or amount to significantly more. The determining that the third data unit is absent from the cache represents an additional step to the mental processes, and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 10 recites: “The method of claim 9, wherein the storing of the prefetch command in the prefetch queue is further based on determining that a prefetch command for the third data is absent from the prefetch queue.” The storing of the prefetch command in the queue based on determining that a prefetch command for the third data is absent from the queue is insignificant extra-solution activity at a high level of generality, and represents well-understood, routine, and conventional activity as shown in [0058-0059] of Park et al., U.S. Pub. No. 20210089457, Col. 12 lines 30-48 of Hakewill et al., U.S. Patent No. 10642618, and [0041] of Kotra et al., U.S. Pub. No. 20220318151. Therefore, this limitation fails to integrate the judicial exceptions into a practical application or amount to significantly more.
Claim 11 recites: “The method of claim 1, further comprising: receiving by the storage device, a cache access sequence, the cache access sequence comprising a prefetch command for a third data unit and a command to place a lock on the third data unit.” The receiving a cache access sequence comprising a prefetch command for a unit and a command to place a lock on the same unit is insignificant extra-solution activity at a high level of generality, and represents well-understood, routine, and conventional activity as shown in Col. 11 line 64 to Col. 12 line 9 of Nakibly et al., U.S. Patent No. 10298496, [0104] of MACNICOL et al., U.S. Pub. No. 20190102412, [0022] of Lewis et al., U.S. Pub. No. 20160019153. Therefore, this limitation fails to integrate the judicial exceptions into a practical application or amount to significantly more.
Claim 12 recites: “The method of claim 11, further comprising performing the prefetch command for the third data unit based on the command to place the lock on the third data unit.” The performing the prefetch command for the third data unit based on the command to place the lock on the third data unit is insignificant extra-solution activity at a high level of generality, and represents well-understood, routine, and conventional activity as shown in Col. 11 line 64 to Col. 12 line 9 of Nakibly et al., U.S. Patent No. 10298496, [0104] of MACNICOL et al., U.S. Pub. No. 20190102412, [0022] of Lewis et al., U.S. Pub. No. 20160019153. Therefore, this limitation fails to integrate the judicial exceptions into a practical application or amount to significantly more.
Claims 13, 15-18 (Statutory Category – Machine)
Step 2A – Prong 1: Judicial Exception Recited?
Claim 13 recites
Select a second data unit for eviction, based on a combination of an eviction algorithm and the command
The limitation of Select a second data unit for eviction, based on a combination of an eviction algorithm and the command, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “the processing circuit being configured to”, nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the “the processing circuit being configured to” language, “Selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command” in the context of this claim encompasses the user mentally observing the data units in the cache, and pointing one out to be the eviction candidate.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A – Prong 2: Integrated into a Practical Application?
This judicial exception is not integrated into a practical application.
In particular, the claim additionally recites the processing circuit being configured to. The processing circuit is recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components (see MPEP 2106.05(f)).
Additionally, other elements recite receive a command to place a lock on a first data unit stored in the cache. The receiving is insignificant extra-solution activity, as they recite a basic receipt of a known command at a high level of generality. The additional elements do not meaningfully limit how the mental process is performed or how it is used in a solution (see MPEP 2106.05(g)).
Additionally, other elements recite a storage device, nonvolatile memory, a processing circuit, a cache. These additional elements amount to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)).
Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: Claim provides an Inventive Concept?
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
As discussed above with respect to Step 2A, the additional limitations are insignificant extra-solution activity, mere instructions to apply judicial exceptions to generic computer components, and generally linking the judicial exception to a particular field of use, and don’t impose any meaningful limits on practicing the abstract idea.
Further, in regards to Step 2B, the additional computer functions have been recognized to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (see MPEP 2106.05(d)(II)).
The additional element of the processing circuit being configured to perform the selecting is a mere instruction to apply the judicial exception using generic computer components, and cannot provide an inventive concept.
The additional elements of a storage device, nonvolatile memory, a processing circuit, a cache are merely generally linking the use of the judicial exception to a particular technological environment and does not provide an inventive concept.
The additional element of receive a command to place a lock on a first data unit stored in the cache covers well-understood, routine, and conventional functions of a basic receiving a known command, which is recited in a merely generic manner, and does not provide an inventive concept. One example of this command to place a lock on a data unit stored in the cache being known in the art is in [0022] and [0027] YAMAMURA et al., U.S. Pub. No. 20090172289, which describes the existence other methods and conventional arts of a programmer performing a locking operation on an area (cache line or cache way) of the cache.
The additional elements have been considered both individually and as an ordered combination in the significantly more consideration.
The claim is ineligible.
Claim 15 recites: “The storage device of claim 13, wherein the selecting of the second data unit for eviction comprises selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the command.” The limitation merely adds another condition to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 16 recites: “The storage device of claim 15, wherein the first data unit is excluded from the set of data units based on the command.” The limitation merely adds another condition to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 17 recites: “The storage device of claim 13, wherein: the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the command.” All of these limitations merely add additional conditions and results to the decision-making and are therefore considered part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 18 recites: “The storage device of claim 17, wherein: the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being the highest-ranked data that is not locked.” These limitations add additional conditions and steps to the decision-making and is therefore considered a part of the judicial exceptions, and cannot integrate the judicial exceptions into a practical application or amount to significantly more than the judicial exceptions.
Claim 19 (Statutory Category – Machine)
Step 2A – Prong 1: Judicial Exception Recited?
Claim 19 recites
Select a second data unit for eviction, based on a combination of an eviction algorithm and the command
The limitation of Select a second data unit for eviction, based on a combination of an eviction algorithm and the command, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “the means for processing being configured to”, nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the “the means for processing being configured to” language, “Selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command” in the context of this claim encompasses the user mentally observing the data units in the cache, and pointing one out to be the eviction candidate.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A – Prong 2: Integrated into a Practical Application?
This judicial exception is not integrated into a practical application.
In particular, the claim additionally recites the means for processing being configured to. The processing circuit is recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components (see MPEP 2106.05(f)).
Additionally, other elements recite receive a command to place a lock on a first data unit stored in the cache. The receiving is insignificant extra-solution activity, as they recite a basic receipt of a known command at a high level of generality. The additional elements do not meaningfully limit how the mental process is performed or how it is used in a solution (see MPEP 2106.05(g)).
Additionally, other elements recite a storage device, nonvolatile memory, means for processing, a cache. These additional elements amount to no more than generally linking the use of a judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)).
Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: Claim provides an Inventive Concept?
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
As discussed above with respect to Step 2A, the additional limitations are insignificant extra-solution activity, mere instructions to apply judicial exceptions to generic computer components, and generally linking the judicial exception to a particular field of use, and don’t impose any meaningful limits on practicing the abstract idea.
Further, in regards to Step 2B, the additional computer functions have been recognized to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (see MPEP 2106.05(d)(II)).
The additional element of the means for processing being configured to perform the selecting is a mere instruction to apply the judicial exception using generic computer components, and cannot provide an inventive concept.
The additional elements of a storage device, nonvolatile memory, means for processing, a cache are merely generally linking the use of the judicial exception to a particular technological environment and does not provide an inventive concept.
The additional element of receive a command to place a lock on a first data unit stored in the cache covers well-understood, routine, and conventional functions of a basic receiving a known command, which is recited in a merely generic manner, and does not provide an inventive concept. One example of this command to place a lock on a data unit stored in the cache being known in the art is in [0022] and [0027] YAMAMURA et al., U.S. Pub. No. 20090172289, which describes the existence other methods and conventional arts of a programmer performing a locking operation on an area (cache line or cache way) of the cache.
The additional elements have been considered both individually and as an ordered combination in the significantly more consideration.
The claim is ineligible.
Examiner notes that claims 2, 8, 14, and 20 are not rejected under 35 U.S.C. 101 because they are considered to be directed to an improvement to the technology, and therefore integrate the judicial exceptions into a practical application. MPEP 2106.05(a) recites “After the examiner has consulted the specification and determined that the disclosed invention improves technology, the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology… That is, the claim must include the components or steps of the invention that provide the improvement described in the specification. However, the claim itself does not need to explicitly recite the improvement described in the specification.” Claims 2, 8, 14, and 20 include limitations to actually perform evictions using the selections previously made, which reflects the process of the invention which provide the improvements described in [0043] and [0065] of the instant specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 13-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”)
Regarding claim 1: Nakibly teaches A method comprising:
Receiving, by a storage device comprising a cache and nonvolatile memory, a command to place a lock on a first data unit stored in the cache; and selecting a second data unit for eviction, based on a combination of an eviction algorithm and the command (Col. 9 lines 53-63, Nakibly teaches that a cache system can receive requests for memory descriptors to the cache, which would then be locked by incrementing a lock counter, and that a lock counter is used to determine which entries can be evicted. Further, in Col. 7 lines 5-7, Col. 9 lines 42-43, Col. 6 lines 36-45, Nakibly teaches that a cache control logic is a cache controller which performs the managing of the caching, eviction, and tracking of the entries using the lock counter. Since the lock counter is taught to be stored in the cache entries and not on the cache control logic (ie. two different components that need communications between them to perform actions), the cache control logic component is interpreted to perform the incrementing of the lock counters on the cache components, and therefore is interpreted to send to the storage device some kind of command to place a lock on the first data unit).
Regarding claim 2: Nakibly teaches all limitations of claim 1, from which claim 2 depends.
Nakibly further teaches performing a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the command, performing a second iteration of the eviction algorithm, the second iteration selecting the second data unit for eviction. (Col. 9 line 67 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Regarding claim 3: Nakibly teaches all limitations of claim 1, from which claim 3 depends.
Nakibly further teaches selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the command (Col. 10 lines 4-15, Nakibly teaches a selection process for an eviction algorithm, that would select an entry based on what is locked.)
Regarding claim 4: Nakibly teaches all limitations of claim 3, from which claim 4 depends.
Nakibly further teaches the first data unit is excluded from the set of data units based on the command. (Col. 10 lines 15-17, Nakibly teaches an embodiment where locked entries in a cache are excluded from being evicted at all.)
Regarding claim 5: Nakibly teaches all limitations of claim 1, from which claim 5 depends.
Nakibly further teaches the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the command. (Col. 10, lines 7-15, Nakibly teaches that each entry of a cache may store LRU information, which the control logic can use to select entries for eviction, which is interpreted to be the data unit characteristics. Further, by describing an entry in a system a full cache (and therefore multiple entries), being selected for eviction when it’s the least-recently-used entry among the unlocked ones, Nakibly teaches a first data unit having a first value of the characteristic, a second data unit having a second value, and a situation where the second data unit is selected for eviction based on the lock command.)
Regarding claim 6: Nakibly teaches all limitations of claim 5, from which claim 6 depends.
Nakibly further teaches the data unit characteristic is based on recency of usage (Col. 10 lines 7-9, Nakibly teaches that the LRU information is a timestamp indicating when the entry was last accessed, which is interpreted as the data unit characteristic being based on recency of usage.)
Regarding claim 7: Nakibly teaches all limitations of claim 5, from which claim 7 depends.
Nakibly further teaches the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being a highest-ranked data unit that is not locked. (Col. 10 lines 9-12, Nakibly teaches that the cache control logic can evict the least-recently-used entry among the unlocked entries based on LRU information. By identifying an entry as the one that is least-recently-used among the entries that are not locked, Nakibly teaches a kind of ranking according to the data unit characteristic and eviction algorithm that selects based on a particular unit being the highest-ranked (least recent) unit that is not locked.)
Regarding claim 8: Nakibly teaches all limitations of claim 1, from which claim 8 depends.
Nakibly further teaches receiving, by the storage device, a command to release the lock on the first data unit (Col. 11 lines 54-63, Nakibly teaches that a cache control logic can decrement a lock counter during an execution stage, and that if an entry’s lock counter becomes zero, it can be later evicted. In combination with Col. 9 lines 50-51, where Nakibly teaches that a zero indicates an unlocking, the teachings of Nakibly teach that the storage device would receive commands which result in releasing the lock on a data unit.)
Nakibly further teaches determining that a cache eviction is needed; and evicting the first data unit (Col. 11 lines 54-63 and Col. 9 line 63 to Col. 10 line 23, Nakibly teaches a case where a previously locked cache entry may become unlocked and then can be evicted, and a process that an additional entry is needed in the cache when the cache is full, and would need to perform a selection and eviction of an entry. In combination, Nakibly teaches the determining a cache eviction is needed, and evicting a first data unit in that case.)
Regarding claim 13: Nakibly teaches A storage device, comprising:
Nonvolatile memory; a processing circuit; and a cache, the processing circuit being configured to (Col. 4 line 52 to Col. 5 line 19 and Col. 6 lines 36-45, Nakibly teaches a storage memory which could be a flash memory and therefore a nonvolatile memory, a cache control logic interfacing with a packet processor which is interpreted to be a processing circuit, and a cache memory.)
Receive a command to place a lock on a first data unit stored in the cache; and select a second data unit for eviction, based on a combination of an eviction algorithm and the command (Col. 9 lines 53-63, Nakibly teaches that a cache system can receive requests for memory descriptors to the cache, which would then be locked by incrementing a lock counter, and that a lock counter is used to determine which entries can be evicted. Further, in Col. 7 lines 5-7, Col. 9 lines 42-43, Col. 6 lines 36-45, Nakibly teaches that a cache control logic is a cache controller which performs the managing of the caching, eviction, and tracking of the entries using the lock counter. Since the lock counter is taught to be stored in the cache entries and not on the cache control logic (ie. two different components that need communications between them to perform actions), the cache control logic component is interpreted to perform the incrementing of the lock counters on the cache components, and therefore is interpreted to send to the storage device some kind of command to place a lock on the first data unit).
Regarding claim 14: Nakibly teaches all limitations of claim 13, from which claim 14 depends.
Nakibly further teaches performing a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the command, performing a second iteration of the eviction algorithm, the second iteration selecting the second data unit for eviction. (Col. 9 line 67 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Regarding claim 15: Nakibly teaches all limitations of claim 13, from which claim 15 depends.
Nakibly further teaches selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the command (Col. 10 lines 4-15, Nakibly teaches a selection process for an eviction algorithm, that would select an entry based on what is locked.)
Regarding claim 16: Nakibly teaches all limitations of claim 15, from which claim 16 depends.
Nakibly further teaches the first data unit is excluded from the set of data units based on the command. (Col. 10 lines 15-17, Nakibly teaches an embodiment where locked entries in a cache are excluded from being evicted at all.)
Regarding claim 17: Nakibly teaches all limitations of claim 13, from which claim 17 depends.
Nakibly further teaches the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the command. (Col. 10, lines 7-15, Nakibly teaches that each entry of a cache may store LRU information, which the control logic can use to select entries for eviction, which is interpreted to be the data unit characteristics. Further, by describing an entry in a system a full cache (and therefore multiple entries), being selected for eviction when it’s the least-recently-used entry among the unlocked ones, Nakibly teaches a first data unit having a first value of the characteristic, a second data unit having a second value, and a situation where the second data unit is selected for eviction based on the lock command.)
Regarding claim 18: Nakibly teaches all limitations of claim 17, from which claim 18 depends.
Nakibly further teaches the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being a highest-ranked data unit that is not locked. (Col. 10 lines 9-12, Nakibly teaches that the cache control logic can evict the least-recently-used entry among the unlocked entries based on LRU information. By identifying an entry as the one that is least-recently-used among the entries that are not locked, Nakibly teaches a kind of ranking according to the data unit characteristic and eviction algorithm that selects based on a particular unit being the highest-ranked (least recent) unit that is not locked.)
Regarding claim 19: Nakibly teaches A storage device, comprising:
Nonvolatile memory; means for processing; and a cache, the means for processing being configured to (Examiner notes that means for processing is being interpreted as any combination of hardware, firmware, software employed to process data or digital signals, according to [0085] of the instant specification. Col. 4 line 52 to Col. 5 line 19 and Col. 6 lines 36-45, Nakibly teaches a storage memory which could be a flash memory and therefore a nonvolatile memory, a cache control logic interfacing with a packet processor which is interpreted to be a processing circuit, and a cache memory.)
Receive a command to place a lock on a first data unit stored in the cache; and select a second data unit for eviction, based on a combination of an eviction algorithm and the command (Col. 9 lines 53-63, Nakibly teaches that a cache system can receive requests for memory descriptors to the cache, which would then be locked by incrementing a lock counter, and that a lock counter is used to determine which entries can be evicted. Further, in Col. 7 lines 5-7, Col. 9 lines 42-43, Col. 6 lines 36-45, Nakibly teaches that a cache control logic is a cache controller which performs the managing of the caching, eviction, and tracking of the entries using the lock counter. Since the lock counter is taught to be stored in the cache entries and not on the cache control logic (ie. two different components that need communications between them to perform actions), the cache control logic component is interpreted to perform the incrementing of the lock counters on the cache components, and therefore is interpreted to send to the storage device some kind of command to place a lock on the first data unit).
Regarding claim 20: Nakibly teaches all limitations of claim 19, from which claim 20 depends.
Nakibly further teaches performing a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the command, performing a second iteration of the eviction algorithm, the second iteration selecting the second data unit for eviction. (Col. 9 line 67 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Shicht et al., U.S. Pub. No. 20220188970 (hereinafter “Shicht”).
Regarding claim 9: Nakibly teaches all limitations of claim 1, from which claim 9 depends.
Nakibly further teaches receiving a prefetch command for a third data unit; determining that the third data unit is absent from the cache… the storing of the prefetch… being based on the determining that the third data unit is absent from the cache. (Col. 7 lines 5-32, Nakibly teaches that a request for memory descriptors results in first checking to see If the requested memory descriptors can be found in the prefetch cache, and if they are not found, controlling the prefetch cache to prefetch the memory descriptors.)
While Nakibly teaches a queue of tasks from which prefetches are made, Nakibly does not appear to explicitly disclose a prefetch queue in which prefetch commands are stored.
However, Shicht teaches storing the prefetch command in a prefetch queue ([0053], Shicht teaches a pre-fetching mechanism that includes a pre-fetch queue, in which pre-fetch requests are placed.)
Nakibly and Shicht are analogous art because they are from the same field of endeavor, cache fetching techniques.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly and Shicht to achieve the result of the method of claim 1, which further receives prefetch commands, determines that the requested data is not present in the cache, and stores the prefetch command in a prefetch queue based on the determination.
One of ordinary skill in the art would have been motivated to make this modification in order to allow the prefetch requests to be processed and stored independent to when they can actually be fulfilled by the cache as discussed in Shicht [0053].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Shicht et al., U.S. Pub. No. 20220188970 (hereinafter “Shicht”) further in view of
Hakewill et al., U.S. Patent No. 10642618 (hereinafter “Hakewill”).
Regarding claim 10: The combination of Nakibly and Shicht teaches all limitations of claim 9, from which claim 10 depends.
Nakibly/Schicht does not appear to explicitly disclose a prefetch queue in which prefetch commands are stored.
However, Hakewill teaches the storing of the prefetch command in the prefetch queue is further based on determining that a prefetch command for the third data unit is absent from the prefetch queue (Col. 12 lines 30-48, Hakewill teaches a prefetch candidate checking method which involves checking if a candidate entry matches one of the entries already in a prefetch queue.)
Nakibly/Shicht and Hakewill are analogous art because they are from the same field of endeavor, cache fetching techniques.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly/Shicht and Hakewill to achieve the result of the method of claim 10, which stores a prefetch command in a prefetch queue based on determining that a prefetch command for the requested data is absent from the prefetch queue.
One of ordinary skill in the art would have been motivated to make this modification in order to avoid redundancy when a request for the same data is already in progress as discussed in Hakewill Col. 12 lines 46-48.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Biederman et al., U.S. Pub. No. 20220116478 (hereinafter “Biederman”).
Regarding claim 11: Nakibly teaches all limitations of claim 1, from which claim 11 depends.
Nakibly further teaches receiving, by the storage device, a cache access sequence, the cache access sequence comprising a prefetch command for a third data unit and a command to place a lock on… data unit. (Col. 7 lines 5-32 and Col. 9 lines 42-60, Nakibly teaches a process in which to perform a packet processing task, there are a sequence of cache accesses that involves caching memory descriptors, which includes the prefetching for data entries and locking of data entries, which is interpreted to be the cache access sequence comprising a prefetch command for the third data unit and a command to place a lock on a data unit.)
Nakibly does not appear to explicitly disclose the process involving the prefetching and locking being performed on the same data unit.
However, Biederman teaches a prefetch command for a third data unit and a command to place a lock on the third data unit ([0139], Biederman teaches a particular process of processing a microservice, in which cache contents that are needed for a next microservice are preloaded and then locked when the microservice is being processed.)
Nakibly and Biederman are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly and Biederman to achieve the result of The method of claim 1, further comprising receiving a cache access sequence involving a prefetch command for a third data unit, and a command to place a lock on the same third data unit.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a process of managing cache locks to optimize a cache for processed a microservice during the specific time it will be processed as discussed in Biederman [0138].
Regarding claim 12: The combination of Nakibly and Biederman teaches all limitations of claim 11, from which claim 12 depends.
Nakibly/Biederman further teaches performing the prefetch command for the third data unit based on the command to place the lock on the third data unit. ([0133-0139], Biederman teaches that, in a system with a known sequence of performing a locking for cache contents, a preloading is performed for new cache contents, which is interpreted to be the claimed prefetching based on the command to place the lock on the data.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
HERDRICH et al., U.S. Pub. No. 20210042228, teaches a system which takes specific requests from an OS or commands for locking a portion of the cache.
Jackson, U.S. Pub. No. 20250181522, teaches a system which automatically locks newly prefetched entries into a cache.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133