DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to amendment of application on 6-JULY-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 8, filed 6-JULY-2026, with respect to objections to the drawings, rejections to canceled claims, and rejections under 35 U.S.C. 101 have been fully considered and are persuasive due to amendments or cancellation. The objections to the drawings, rejections to canceled claims, and rejections under 35 U.S.C. 101 have been withdrawn.
Applicant has canceled claims 2, 14, and 20, and therefore all rejections have been withdrawn.
Applicant has amended independent claims to include subject matter previously identified to integrate the judicial exceptions into a practical application, by fully incorporating the steps which yield the improvement to the technology outlined in the specification.
Applicant’s arguments, see pages 10-13, filed 6-JULY-2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C 102/35 U.S.C. 103 have been fully considered and are persuasive due to amendment. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previously cited but not applied prior art references.
Regarding applicant’s arguments that Nakibly does not disclose the newly amended limitations of a second command to place a lock as part of a prefetch thread, Examiner agrees. As discussed in the rejections below, the claim is now rejected in view of additional prior art which addresses the new amendments.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 13, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Jackson, U.S. Pub. No. 20250181522 (hereinafter “Jackson”).
Regarding claim 1: Nakibly teaches A method comprising:
Receiving, by a storage device comprising a cache and nonvolatile memory, as part of a prefetch thread, a first command to prefetch a first data unit stored in the cache… (Col. 6 line 36 to Col. 7 line 45, Nakibly teaches a system of processing prefetch requests for memory descriptors into a cache).
a lock on the first data unit stored in the cache; performing a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the lock, performing a second iteration of the eviction algorithm, the second iteration selecting a second data unit for eviction. (Col. 9 line 42 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved due to a lock on the data, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Although Nakibly teaches lock counters in a cache being incremented by a controller, Nakibly does not appear to explicitly disclose as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache.
However, Jackson teaches as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache ([0058-0059], Jackson teaches that as part of a prefetching process, a cache controller can automatically lock the newly prefetched cache line.).
Nakibly and Jackson are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly and Jackson to achieve the result of a system which prefetches a first data unit and locks the first data unit as part of a prefetch process, then performs an eviction algorithm where the first iteration selects the first data unit, but based on the lock command, performs a second iteration of eviction selecting the second data unit for eviction.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce execution times for programs by protecting certain cache lines from eviction as discussed in Jackson [0036-0037].
Regarding claim 3: The combination of Nakibly and Jackson teaches all limitations of claim 1, from which claim 3 depends.
Nakibly/Jackson further teaches selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the second command (Col. 10 lines 4-15, Nakibly teaches a selection process for an eviction algorithm, that would select an entry based on what is locked.)
Regarding claim 4: The combination of Nakibly and Jackson teaches all limitations of claim 3, from which claim 4 depends.
Nakibly/Jackson further teaches the first data unit is excluded from the set of data units based on the second command. (Col. 10 lines 15-17, Nakibly teaches an embodiment where locked entries in a cache are excluded from being evicted at all.)
Regarding claim 5: The combination of Nakibly and Jackson teaches all limitations of claim 1, from which claim 5 depends.
Nakibly/Jackson further teaches the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the second command. (Col. 10, lines 7-15, Nakibly teaches that each entry of a cache may store LRU information, which the control logic can use to select entries for eviction, which is interpreted to be the data unit characteristics. Further, by describing an entry in a system a full cache (and therefore multiple entries), being selected for eviction when it’s the least-recently-used entry among the unlocked ones, Nakibly teaches a first data unit having a first value of the characteristic, a second data unit having a second value, and a situation where the second data unit is selected for eviction based on the lock command.)
Regarding claim 6: The combination of Nakibly and Jackson teaches all limitations of claim 5, from which claim 6 depends.
Nakibly/Jackson further teaches the data unit characteristic is based on recency of usage (Col. 10 lines 7-9, Nakibly teaches that the LRU information is a timestamp indicating when the entry was last accessed, which is interpreted as the data unit characteristic being based on recency of usage.)
Regarding claim 7: The combination of Nakibly and Jackson teaches all limitations of claim 5, from which claim 7 depends.
Nakibly/Jackson further teaches the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being a highest-ranked data unit that is not locked. (Col. 10 lines 9-12, Nakibly teaches that the cache control logic can evict the least-recently-used entry among the unlocked entries based on LRU information. By identifying an entry as the one that is least-recently-used among the entries that are not locked, Nakibly teaches a kind of ranking according to the data unit characteristic and eviction algorithm that selects based on a particular unit being the highest-ranked (least recent) unit that is not locked.)
Regarding claim 8: The combination of Nakibly and Jackson teaches all limitations of claim 1, from which claim 8 depends.
Nakibly/Jackson further teaches receiving, by the storage device, a third command to release the lock on the first data unit (Col. 11 lines 54-63, Nakibly teaches that a cache control logic can decrement a lock counter during an execution stage, and that if an entry’s lock counter becomes zero, it can be later evicted. In combination with Col. 9 lines 50-51, where Nakibly teaches that a zero indicates an unlocking, the teachings of Nakibly teach that the storage device would receive commands which result in releasing the lock on a data unit.)
Nakibly/Jackson further teaches determining that a cache eviction is needed; and evicting the first data unit (Col. 11 lines 54-63 and Col. 9 line 63 to Col. 10 line 23, Nakibly teaches a case where a previously locked cache entry may become unlocked and then can be evicted, and a process that an additional entry is needed in the cache when the cache is full, and would need to perform a selection and eviction of an entry. In combination, Nakibly teaches the determining a cache eviction is needed, and evicting a first data unit in that case.)
Regarding claim 13: Nakibly teaches A storage device, comprising:
Nonvolatile memory; a processing circuit; and a cache, the processing circuit being configured to (Col. 4 line 52 to Col. 5 line 19 and Col. 6 lines 36-45, Nakibly teaches a storage memory which could be a flash memory and therefore a nonvolatile memory, a cache control logic interfacing with a packet processor which is interpreted to be a processing circuit, and a cache memory.)
Receive, as part of a prefetch thread, a first command to prefetch a first data unit stored in the cache… (Col. 6 line 36 to Col. 7 line 45, Nakibly teaches a system of processing prefetch requests for memory descriptors into a cache).
a lock on the first data unit stored in the cache; perform a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the lock, perform a second iteration of the eviction algorithm, the second iteration selecting a second data unit for eviction. (Col. 9 line 42 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved due to a lock on the data, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Although Nakibly teaches lock counters in a cache being incremented by a controller, Nakibly does not appear to explicitly disclose as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache.
However, Jackson teaches as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache ([0058-0059], Jackson teaches that as part of a prefetching process, a cache controller can automatically lock the newly prefetched cache line.).
Nakibly and Jackson are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly and Jackson to achieve the result of a system which prefetches a first data unit and locks the first data unit as part of a prefetch process, then performs an eviction algorithm where the first iteration selects the first data unit, but based on the lock command, performs a second iteration of eviction selecting the second data unit for eviction.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce execution times for programs by protecting certain cache lines from eviction as discussed in Jackson [0036-0037].
Regarding claim 15: The combination of Nakibly and Jackson teaches all limitations of claim 13, from which claim 15 depends.
Nakibly/Jackson further teaches selecting, by the eviction algorithm, the second data unit from a set of data units determined based on the second command (Col. 10 lines 4-15, Nakibly teaches a selection process for an eviction algorithm, that would select an entry based on what is locked.)
Regarding claim 16: The combination of Nakibly and Jackson teaches all limitations of claim 15, from which claim 16 depends.
Nakibly/Jackson further teaches the first data unit is excluded from the set of data units based on the second command. (Col. 10 lines 15-17, Nakibly teaches an embodiment where locked entries in a cache are excluded from being evicted at all.)
Regarding claim 17: The combination of Nakibly and Jackson teaches all limitations of claim 13, from which claim 17 depends.
Nakibly/Jackson further teaches the eviction algorithm targets a data unit characteristic, the first data unit has a first value of the data unit characteristic, the second data unit has a second value of the data unit characteristic, the algorithm is configured to select the first data unit based on the first value and the second value, and the second data unit is selected for eviction based on the second command. (Col. 10, lines 7-15, Nakibly teaches that each entry of a cache may store LRU information, which the control logic can use to select entries for eviction, which is interpreted to be the data unit characteristics. Further, by describing an entry in a system a full cache (and therefore multiple entries), being selected for eviction when it’s the least-recently-used entry among the unlocked ones, Nakibly teaches a first data unit having a first value of the characteristic, a second data unit having a second value, and a situation where the second data unit is selected for eviction based on the lock command.)
Regarding claim 18: The combination of Nakibly and Jackson teaches all limitations of claim 17, from which claim 18 depends.
Nakibly/Jackson further teaches the eviction algorithm ranks a plurality of data units, including the first data unit and the second data unit, according to the data unit characteristic, and the eviction algorithm selects the second data unit based on the second data unit being a highest-ranked data unit that is not locked. (Col. 10 lines 9-12, Nakibly teaches that the cache control logic can evict the least-recently-used entry among the unlocked entries based on LRU information. By identifying an entry as the one that is least-recently-used among the entries that are not locked, Nakibly teaches a kind of ranking according to the data unit characteristic and eviction algorithm that selects based on a particular unit being the highest-ranked (least recent) unit that is not locked.)
Regarding claim 19: Nakibly teaches A storage device, comprising:
Nonvolatile memory; means for processing; and a cache, the means for processing being configured to (Examiner notes that means for processing is being interpreted as any combination of hardware, firmware, software employed to process data or digital signals, according to [0085] of the instant specification. Col. 4 line 52 to Col. 5 line 19 and Col. 6 lines 36-45, Nakibly teaches a storage memory which could be a flash memory and therefore a nonvolatile memory, a cache control logic interfacing with a packet processor which is interpreted to be a processing circuit, and a cache memory.)
Receive, as part of a prefetch thread, a first command to prefetch a first data unit stored in the cache… (Col. 6 line 36 to Col. 7 line 45, Nakibly teaches a system of processing prefetch requests for memory descriptors into a cache).
a lock on the first data unit stored in the cache; perform a first iteration of the eviction algorithm, the first iteration selecting the first data unit; and based on the lock, perform a second iteration of the eviction algorithm, the second iteration selecting a second data unit for eviction. (Col. 9 line 42 to Col. 10 line 12, Nakibly teaches an example of an eviction determination, where the control logic first specifically determines that one entry should be preserved due to a lock on the data, then instead evicts a different entry that is unlocked. While not explicitly stated as iterations of an eviction algorithm, the sequence of determining specifically that one entry should not be evicted, then afterwards determining a different entry should be evicted instead is interpreted to be the claimed first and second iterations.)
Although Nakibly teaches lock counters in a cache being incremented by a controller, Nakibly does not appear to explicitly disclose as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache.
However, Jackson teaches as part of a prefetch thread… a second command to place a lock on the first data unit stored in the cache ([0058-0059], Jackson teaches that as part of a prefetching process, a cache controller can automatically lock the newly prefetched cache line.).
Nakibly and Jackson are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly and Jackson to achieve the result of a system which prefetches a first data unit and locks the first data unit as part of a prefetch process, then performs an eviction algorithm where the first iteration selects the first data unit, but based on the lock command, performs a second iteration of eviction selecting the second data unit for eviction.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce execution times for programs by protecting certain cache lines from eviction as discussed in Jackson [0036-0037].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Jackson, U.S. Pub. No. 20250181522 (hereinafter “Jackson”) further in view of
Shicht et al., U.S. Pub. No. 20220188970 (hereinafter “Shicht”).
Regarding claim 9: The combination of Nakibly and Jackson teaches all limitations of claim 1, from which claim 9 depends.
Nakibly/Jackson further teaches receiving a prefetch command for a third data unit; determining that the third data unit is absent from the cache… the storing of the prefetch… being based on the determining that the third data unit is absent from the cache. (Col. 7 lines 5-32, Nakibly teaches that a request for memory descriptors results in first checking to see If the requested memory descriptors can be found in the prefetch cache, and if they are not found, controlling the prefetch cache to prefetch the memory descriptors.)
While Nakibly teaches a queue of tasks from which prefetches are made, Nakibly/Jackson does not appear to explicitly disclose a prefetch queue in which prefetch commands are stored.
However, Shicht teaches storing the prefetch command in a prefetch queue ([0053], Shicht teaches a pre-fetching mechanism that includes a pre-fetch queue, in which pre-fetch requests are placed.)
Nakibly/Jackson and Shicht are analogous art because they are from the same field of endeavor, cache fetching techniques.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly/Jackson and Shicht to achieve the result of the method of claim 1, which further receives prefetch commands, determines that the requested data is not present in the cache, and stores the prefetch command in a prefetch queue based on the determination.
One of ordinary skill in the art would have been motivated to make this modification in order to allow the prefetch requests to be processed and stored independent to when they can actually be fulfilled by the cache as discussed in Shicht [0053].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Jackson, U.S. Pub. No. 20250181522 (hereinafter “Jackson”) further in view of
Shicht et al., U.S. Pub. No. 20220188970 (hereinafter “Shicht”) further in view of
Hakewill et al., U.S. Patent No. 10642618 (hereinafter “Hakewill”).
Regarding claim 10: The combination of Nakibly, Jackson, and Shicht teaches all limitations of claim 9, from which claim 10 depends.
Nakibly/Jackson/Schicht does not appear to explicitly disclose a prefetch queue in which prefetch commands are stored.
However, Hakewill teaches the storing of the prefetch command in the prefetch queue is further based on determining that a prefetch command for the third data unit is absent from the prefetch queue (Col. 12 lines 30-48, Hakewill teaches a prefetch candidate checking method which involves checking if a candidate entry matches one of the entries already in a prefetch queue.)
Nakibly/Jackson/Shicht and Hakewill are analogous art because they are from the same field of endeavor, cache fetching techniques.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly/Jackson/Shicht and Hakewill to achieve the result of the method of claim 10, which stores a prefetch command in a prefetch queue based on determining that a prefetch command for the requested data is absent from the prefetch queue.
One of ordinary skill in the art would have been motivated to make this modification in order to avoid redundancy when a request for the same data is already in progress as discussed in Hakewill Col. 12 lines 46-48.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over
Nakibly et al., U.S. Patent No. 10298496 (hereinafter “Nakibly”) in view of
Jackson, U.S. Pub. No. 20250181522 (hereinafter “Jackson”) further in view of
Biederman et al., U.S. Pub. No. 20220116478 (hereinafter “Biederman”).
Regarding claim 11: The combination of Nakibly and Jackson teaches all limitations of claim 1, from which claim 11 depends.
Nakibly/Jackson further teaches receiving, by the storage device, a cache access sequence, the cache access sequence comprising a prefetch command for a third data unit and a command to place a lock on… data unit. (Col. 7 lines 5-32 and Col. 9 lines 42-60, Nakibly teaches a process in which to perform a packet processing task, there are a sequence of cache accesses that involves caching memory descriptors, which includes the prefetching for data entries and locking of data entries, which is interpreted to be the cache access sequence comprising a prefetch command for the third data unit and a command to place a lock on a data unit.)
Nakibly/Jackson does not appear to explicitly disclose the process involving the prefetching and locking being performed on the same data unit.
However, Biederman teaches a prefetch command for a third data unit and a command to place a lock on the third data unit ([0139], Biederman teaches a particular process of processing a microservice, in which cache contents that are needed for a next microservice are preloaded and then locked when the microservice is being processed.)
Nakibly/Jackson and Biederman are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nakibly/Jackson and Biederman to achieve the result of The method of claim 1, further comprising receiving a cache access sequence involving a prefetch command for a third data unit, and a command to place a lock on the same third data unit.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a process of managing cache locks to optimize a cache for processed a microservice during the specific time it will be processed as discussed in Biederman [0138].
Regarding claim 12: The combination of Nakibly, Jackson, and Biederman teaches all limitations of claim 11, from which claim 12 depends.
Nakibly/Jackson/Biederman further teaches performing the prefetch command for the third data unit based on the command to place the lock on the third data unit. ([0133-0139], Biederman teaches that, in a system with a known sequence of performing a locking for cache contents, a preloading is performed for new cache contents, which is interpreted to be the claimed prefetching based on the command to place the lock on the data.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 11.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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