Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 5-8, and 10-20 is/are rejected under 102(a)(1) as being anticipated by
Tech Pathfinder, “ Small Size, Big Impact: Unveiling the Latest Advances in Semiconductor Packaging and Miniaturization,” hereafter Tech Pathfinder
As per claim 1, 8, and 17, Tech Pathfinder teaches a system-in-package (SiP) device (“ Known as a system-in-package (SiP), it fundamentally needs miniaturization as well as advanced packaging technology, see pg. 2), comprising: a base substrate; a processing unit carried by the base substrate; a high bandwidth memory (HBM) device carried by the base substrate and electrically coupled to the processing unit through a SiP bus, wherein the HBM device comprises: a first interface die; one or more volatile memory dies carried by the first interface die; an dan HBM bus electrically coupled to the first interface die and each of the one or more volatile memory dies (See pg. 8, “ stack multiple chips and package them. It is used commonly in High Bandwidth Memory (HBM), which increases the number of data paths, or bandwidth, by stacking multiple DRAM chips with TSV (Through-Silicon Via)7. The thousands of data paths that vertically run through the stacked chips are connected without wiring and are later wrapped with MR-MUF.”); and a high bandwidth storage (HBS) (part of SK Hynix’s Chiplet, multi-chip packaging (MCP), vertical wire fan-out (VFO), and advanced mass reflow-molded underfill (MR-MUF) are some of the main technologies for heterogeneous integration), device carried by the base substrate and electrically coupled to the HBM device through the SiP bus (See pg. 8, “ stack multiple chips and package them. It is used commonly in High Bandwidth Memory (HBM), which increases the number of data paths, or bandwidth, by stacking multiple DRAM chips with TSV (Through-Silicon Via)7, wherein the HBS device comprises: a second interface die; one or more non-volatile memory dies carried by the second interface die; and an HBS bus electrically coupled to the second interface die and each of the one or more non-volatile memory dies.
Tech Pathfinder discloses a type of HBS by teaching about SK Hynix’s Chiplet, multi-chip packaging (MCP), and vertical wire fan-out (VFO) specific advanced packaging technology used to build HBM produces. Tech Pathfinder describes how the SK Hynix’s ‘HBS’ specializes in stacking memory products like NAND and DRAM, stacks NAND and DRAM wherein enabling higher bandwidth and performance by Vertical wire fan-out (VFO). The VFO is key for enabling technology HBS as it is the packaging method that makes for and is used to HBM products, enabling higher bandwidth and performance. Further, it is worth noting that unlike HBM, HBS does not require through-silicon via (TSV) processes that penetrate the chip, giving it higher yields and lower manufacturing costs. (See entire article)
As per claim 2, Tech Pathfinder discloses wherein the second interface die includes a storage controller, the storage controller configured to: receive a request for a subset of a data set stored in the one or more non-volatile memory dies; read the subset of the data set from the non-volatile memory dies; and send a copy of the subset of the data set dies to the one or more volatile memory dies in the HBM device. (See entire article Figs. 1-2)
As per claim 3, Tech Pathfinder discloses wherein the HBS device further comprises a volatile memory die carried by the second interface die and electrically coupled to the HBS bus. (See entire article Figs. 1-2)
As per claim 5, Tech Pathfinder discloses wherein the SiP bus comprises: a first portion electrically coupled between the processing unit and the HBM device, wherein the first portion has a first bandwidth; and a second portion electrically coupled between the HBM device and the HBS device, wherein the second portion has a second bandwidth generally equal to the first bandwidth. (See entire article Figs. 1-2)
As per claim 6, Tech Pathfinder discloses wherein the HBS device is directly electrically coupled to the processing unit through the SiP bus. (See entire article Figs. 1-2)
As per claim 7, Tech Pathfinder discloses wherein the one or more non-volatile memory dies in the HBS device are configured to provide a non-volatile copy of data stored in the one or more volatile memory dies in the HBM device accessible to the one or more volatile memory dies via the SiP bus in response to a power-up request. (See entire article Figs. 1-2)
As per claims 10-16, and 17-20, see the rejection above.
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The allowable claim language is “..wherein the second interface die includes a storage controller, the storage controller configured to: receive a first request for a subset of a data set stored in the one or more non-volatile memory dies; write a copy of the subset of the data set from the one or more non-volatile memory dies to the volatile memory die carried in the HBS device; receive a second request for the subset of the data set; and send a copy of the subset of the data set from the volatile memory die carried in the HBS device to the one or more volatile memory dies in the HBM device.
Conclusion
RELEVENT ART CITED BY THE EXAMINER - The following prior art made of record and relied upon is citied in PTO-892 to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tammara Peyton whose telephone number is (571) 272-4157. The examiner can normally be reached between 8:30- 6:00 from Monday to Thursday, (I am off every first Friday), and 7:30- 4:00 every second Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Henry Tsai can be reached on (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Any inquiry of a general nature of relating to the status of this application should be directed to the Group receptionist whose telephone number is (571) 272- 2100.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 May 18, 2025
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