Prosecution Insights
Last updated: September 17, 2026
Application No. 19/007,483

Electrically Conducting Structure for Flexible Circuit Board

Non-Final OA §101§102§103
Filed
Jan 01, 2025
Priority
Feb 23, 2024 — TW TW113106693
Examiner
LEE, PETE T
Art Unit
Tech Center
Assignee
Dongguan Kangxiang Electronic Co. Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
605 granted / 807 resolved
+15.0% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
15 currently pending
Career history
822
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
60.0%
+20.0% vs TC avg
§102
23.4%
-16.6% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 807 resolved cases

Office Action

§101 §102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Objections Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “ form” in line 12 is believed to be a typo. Appropriate correction is required. Claim 2 objected to because of the following informalities: Claim 1 recites the limitation “ thru” in line 3 is believed to be a typo. Appropriate correction is required. Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. Pursuant to 37 CFR 1.78(f), when two or more applications filed by the same applicant or assignee contain patentably indistinct claims, elimination of such claims from all but one application may be required in the absence of good and sufficient reason for their retention during pendency in more than one application. Applicant is required to either cancel the patentably indistinct claims from all but one application or maintain a clear line of demarcation between the applications. See MPEP § 822. Claims 1-8 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1-8 of copending Application No. 19/007,485 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim (s) 1-4 and 6-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida et al. (JP 2016127205 A) hereinafter Yoshida. Regarding claim 1, Yoshida discloses, in Fig.3a-Fig.3b, an electrically conducting structure for a flexible circuit board (30) ,comprising: a flexible substrate (30) , having a first surface (top surface of 32), a second surface (bottom surface of 32), a lateral surface (end surface at 32) and a plurality of grooves (34), wherein the first surface is opposite to the second surface, and the lateral surface connects the first surface and the second surface (end surface of 32 connects the top and bottom surface), the grooves (34) are formed on the lateral surface and connect the first surface and the second surface; a circuit layer (top surface of conductor 31), formed on the first surface and comprising at least a conductive structure ( conductor layer in groove 34) located near the lateral surface; at least a soldering structure ( bottom layer of 21 that connects solder;Fig.3b), formed on the second surface; and an electrically connecting structure ( conductor in groove 34), connecting the conductive structure and the soldering structure and extending form the first surface to the second surface ( conductor in groove34 connects the top conductor 31 with the bottom conductor 31). Regarding claim 2, Yoshida discloses wherein the flexible substrate comprising at least one thru hole (33;Fig.3), the at least thru hole going thru the flexible substrate (32) and connects the first surface and the second surface (33 goes through top and bottom surfaces of 32), the electrically connecting structure (31) is formed on the wall of the at least thru hole ( through hole 33 is plated with conductive layer 31) and connects the at least conductive structure and the at least soldering structure ( top layer 31 and bottom layer is connected by 33;Fig.3b). Regarding claim 3, Yoshida discloses wherein the electrically connecting structure comprises at least one conductive layer (see 31 in Fig.3b) and the at least one conductive layer is formed on the wall of at least one groove ( conductive layer is plated in groove of 34;Fig.3a and 3b)), and the at least one conductive layer connects the at least one conductive structure and the at least one soldering structure (see Fig.3b). Regarding claim 4, Yoshida discloses wherein the electrically connecting structure comprises a plurality of the conductive layers, and the plurality of the conductive layers are formed on the wall of the at least one groove (see left to right conductive grooves 34 and conductive layers 31;Fig.3a). Regarding claim 6, Yoshida discloses wherein the electrically conductive structure is a metal bump disposed on the first surface ( see top layer of 31 as a metal bump). Regarding claim 7, Yoshida discloses wherein the electrically conductive structure is a metal bump disposed on the second surface (see bottom layer of 31 as a metal bump). Regarding claim 8, Yoshida discloses wherein the electrically conductive structure is a conductive node (see top layer 31 is a conductive node ) disposed on the first surface ( top surface of 32). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida as applied to claim 1 above, and further in view of Lang et al. (US 2017/0111993 A1) hereinafter Lang. Regarding claim 5, Yoshida is silent with respect to wherein the flexible substrate further comprises at least one accommodating recess, and the at least one accommodating recess is formed is formed on the first surface, the at least one conductive structure is disposed in the at least one accommodating recess, and the at least one conductive structure is flush with the first surface. Lang discloses a substrate (3; Fig.3A) further comprises at least one accommodating recess ( recess that accommodates 31a) , and the at least one accommodating recess is formed is formed on the first surface (32), the at least one conductive structure (31a or 31k) is disposed in the at least one accommodating recess, and the at least one conductive structure is flush with the first surface (see 31a formed flush with top surface of 32;Fig.3A). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Lang to modify the device of Yoshida in order to make the footprint of the flexible substrate device more compact in order to fit into tighter spaces of electrical devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /PETE T LEE/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jan 01, 2025
Application Filed
Sep 08, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
86%
With Interview (+10.9%)
2y 5m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 807 resolved cases by this examiner. Grant probability derived from career allowance rate.

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