Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending.
The IDS, filed 1/2/25, has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Apparatus, Controller, and Method For Managing Overlapping Writes.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhatia (US20230214249).
As to claim 1, Bhatia teaches a data storage apparatus (computing devices; 0019, 0080) comprising:
a memory device (storage devices 134, 0026, 0027); and
a memory controller (storage controller; 0026, 0027) configured to determine that at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus overlaps (determine write operation result in overlapping addresses; 0015, 0055, 0056, 0074), and
execute, in response to a first write request including a first logical addresses received at a first timing (receive write requests from agents; 0015, 0020-0022), an overlap write mode in which data corresponding to a logical address, which non-overlaps a second logical addresses included in a second write request received subsequent to the first write request at a second timing, is programmed in the memory device while deferring programming data of an overlapping logical address (if overlapping addresses, perform only write to non-overlapping addresses; 0015, 0074; write to overlapping addresses is not allowed and retried later; 0071, claim 5).
As to claim 2/10, Bhatia teaches the memory controller is configured to determine whether the at least a portion of the logical addresses overlaps when each write request includes a plurality of logical addresses (determine overlap in write address range; 0015, 0042, 0045, 0058, 0060).
As to claim 3/11, Bhatia teaches the memory controller determines that the at least a portion of the logical addresses overlaps when a leading address of the second logical addresses is equal to or less than a last address of the first logical addresses (determine overlap in write address range, in which overlap occurs when the addresses are within the same range (i.e. greater than a first address and less than a last address); 0015, 0042, 0045, 0058, 0060, 0074).
As to claim 4/12, Bhatia teaches the memory controller is configured to enable and execute the overlap write mode when the at least a portion of the logical addresses overlaps, and disable the overlap write mode when a request other than the write requests is received from the external apparatus (operate in write mode to perform overlap write; 0015, 0074; when in operating in read mode to perform read, write mode/operation is inherently not active/used; 0014, 0024, 0041, 0058-0070).
As to claim 5/13, Bhatia teaches the request other than the write requests includes at least one of a read command (read request processing; 0058-0071), a manager command of the external apparatus, a management command corresponding to power loss of the external apparatus, a reset command, and a command related to error processing.
As to claim 6/8/14, Bhatia teaches when a read command is received from the external apparatus while executing the overlap write mode, the memory controller is configured to program programming-deferred data, and execute the read command (after write operation completes in overlapping range, read operation can be directed to new data; 0077).
As to claim 7, Bhatia teaches a memory controller (storage controller; 0026, 0027) comprising:
an overlap write manager (volume driver manages read/write requests to storage; 0051-0058) configured to: determine whether at least a portion of logical addresses included in adjacent write requests (receive write requests from agents; 0015, 0020-0022) in a sequence of write requests continuously received from an external apparatus overlaps (determine write operation result in overlapping addresses; 0015, 0055, 0056, 0074); and defer, based on a first write request including a first logical addresses received at a first timing and a second logical addresses included in a second write request received subsequent to the first write request at a second timing, writing data corresponding to the first logical addresses of the first write request, the data to be updated (if overlapping addresses, perform only write to non-overlapping addresses; 0015, 0074; write to overlapping addresses is not allowed and retried later; 0071, claim 5).
As to claim 9, Bhatia teaches an operating method (method to manage access to storage; 0015, 0052, claims) of a data storage apparatus, the operating method comprising:
determining whether at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus (receive write requests from agents; 0015, 0020-0022), overlaps (; executing an overlap write mode in response to a determination that the at least a portion of the logical addresses overlaps (determine write operation result in overlapping addresses; 0015, 0055, 0056, 0074); during the overlap write mode, controlling, in response to a first write request including a first logical addresses received at the first timing, data corresponding to a logical address which non-overlaps a second logical addresses included in a second write request received subsequent to the first write request at a second timing, to be programmed while deferring programming data corresponding to a logical address of the first logical addresses, which overlaps the second logical addresses (if overlapping addresses, perform only write to non-overlapping addresses; 0015, 0074; write to overlapping addresses is not allowed and retried later; 0071, claim 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138