DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Serttek (US 2024/0405729) in view of Joshi (US 2007/0274140).
Regarding claim 1, fig. 1 of Serttek discloses a switch device, comprising: a receiving circuit [7b, 8b], coupled between a first terminal [at ANT] and a second terminal [at RX], and comprising: a receiving series circuit [7b], wherein a first terminal of the receiving series circuit is coupled to the first terminal, a second terminal of the receiving series circuit is coupled to the second terminal. Serttek does not disclose the details of the series circuit as claimed. However, fig. 3 of Joshi discloses a series circuit comprising a plurality of receiving series transistors connected in series [N5 and N2], and the receiving series transistors are composed of at least one first receiving series transistor [e.g. N5] and at least one second receiving series transistor [N2]; wherein when the switch device executes a first mode, the at least one first receiving series transistor is turned on to provide a charge release path (See Table 2), and the at least one second receiving series transistor is cut off; and when the switch device executes a second mode, the at least one first receiving series transistor is turned on, and the at least one second receiving series transistor is turned on (See Table 2). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the switching as taught in Joshi into the series FETs 7a, 7b, 8a, and 8b of Serttek for the purpose of utilizing a suitable and well-known type of serial switching.
Regarding claim 2, the combination as indicated above discloses wherein a ratio of a number of the at least one first receiving series transistor to a number of the at least one second receiving series transistor is greater than or equal to 0.2 and less than or equal to 5 (where the ratio is 1).
Regarding claim 3, the combination as indicated above discloses wherein the at least one second receiving series transistor [N2] is coupled to the first terminal, the at least one first receiving series transistor [N5] is coupled between the at least one second receiving series transistor and the second terminal.
Regarding claim 4, the combination as indicated above discloses wherein the receiving circuit further comprising: a first receiving shunt circuit [8b], wherein a first terminal of the first receiving shunt circuit is coupled between the second terminal of the receiving series circuit and the second terminal, a second terminal of the first receiving shunt circuit is coupled to a first reference voltage terminal, and the first receiving shunt circuit is composed of one or a plurality of first receiving shunt transistors connected in series; wherein when the switch device executes the first mode, the one or plurality of first receiving shunt transistors are all turned on; and when the switch device executes the second mode, at least part of the one or plurality of first receiving shunt transistors are cut off.
Regarding claim 5, the combination as indicated above discloses a bypass circuit, coupled between the first terminal and a third terminal, and comprising: a bypass series circuit [e.g. 7a], wherein a first terminal of the bypass series circuit is coupled to the first terminal, a second terminal of the bypass series circuit is coupled to the third terminal, and the bypass series circuit is composed of a plurality of bypass series transistors connected in series; and a bypass shunt circuit [e.g. 8a], wherein a first terminal of the bypass shunt circuit is coupled between the second terminal of the bypass series circuit and the third terminal, a second terminal of the bypass shunt circuit is coupled to a second reference voltage terminal, and the bypass shunt circuit is composed of a plurality of bypass shunt transistors connected in series; wherein when the switch device executes the first mode, the plurality of bypass series transistors are turned on, and the plurality of bypass shunt transistors are cut off; and when the switch device executes the second mode, the plurality of bypass series transistors are cut off, and the plurality of bypass shunt transistors are turned on.
Regarding claim 6, the combination as indicated above discloses a transmitting circuit, coupled between the first terminal and a fourth terminal, and comprising: a transmitting series circuit [7a], wherein a first terminal of the transmitting series circuit is coupled to the first terminal, a second terminal of the transmitting series circuit is coupled to the fourth terminal, and the transmitting series circuit is composed of a plurality of transmitting series transistors connected in series; and a transmitting shunt circuit [8a], wherein a first terminal of the transmitting shunt circuit is coupled between the second terminal of the transmitting series circuit and the fourth terminal, a second terminal of the transmitting shunt circuit is coupled to a reference voltage terminal, and the transmitting shunt circuit is composed of a plurality of transmitting shunt transistors connected in series; and a controlling circuit, providing a first control signal to control the plurality of transmitting shunt transistors and the at least one first receiving series transistor to perform the same operation.
Regarding claim 17, the combination as indicated above discloses a low noise amplifier [2 of fig. 1A of Serttek], wherein the second terminal is coupled to an input terminal of the low noise amplifier, and when the switch device executes the second mode, the receiving circuit is configured to receive a first signal from the first terminal and transmit the first signal to the second terminal, so that the first signal is transmitted to the low noise amplifier.
Regarding claim 18, the combination as indicated above discloses a low noise amplifier [2 of fig. 1A of Serttek], wherein the second terminal is coupled to an input terminal of the low noise amplifier, the third terminal is coupled to an output terminal of the low noise amplifier, and when the switch device executes the first mode, the bypass circuit is configured to receive a first signal from the first terminal and transmit the first signal to the third terminal, so that the first signal is not amplified by the low noise amplifier.
Regarding claim 19, the combination as indicated above discloses an amplifier [1 of fig. 1A of Serttek], wherein an output terminal of the amplifier is coupled to the fourth terminal, and when the switch device executes a third mode, the transmitting circuit is configured to receive a second signal from the fourth terminal and transmit the second signal to the first terminal.
Regarding claim 20, this claim is merely a method to operate the circuit having structure recited in claim 1. Since Serttek in view of Joshi above teaches the structure, the method to operate such a circuit is similarly disclosed.
Allowable Subject Matter
Claims 7-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SIBIN CHEN/ Primary Examiner, Art Unit 2836
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