DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because of the use of unclear or inexact terms “AISC,” “SMT.” A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: “AISC”, “SMT.”
Claim Objections
Claims 3 and 4 are objected to because of the following informalities:
Claim 3, line 2 recites “which” and should recite “which is.”
Claim 4, line 2 recites “which” and should recite “which is.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 17-18 recites the limitation "the second chip assembly is electrically coupled with the first alignment." There is insufficient antecedent basis for this limitation in the claim.
For examination purposes “the first alignment” will be read as “the first alignment layer.”
Claim(s) 2-8 are rejected due to dependency from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Vos et al (hereinafter Vos), US-PG-PUB No. 2015/0251898 in view of Harada et al (hereinafter Harada), US Patent No. 9,668,362.
Regarding claim 1, Vos teaches a microphone (A mems microphone…..¶[0020]), comprising:
a shell (Shown in Fig. 1 and detailed in ¶[0028], shell (107));
a printed circuit board (108) covered and fixed with the shell and enclosing a cavity together with the shell (Shown in Fig. 1, shell (107) forms an enclosure/cavity as it is on top of PCB (108));
a first chip assembly (MEMS die 102) fixed with a side of the printed circuit board close to the shell and accommodated in the cavity (Visible in Fig. 1);
and a second chip assembly embedded (Integrated circuit 104) and accommodated in the printed circuit board (Visible in Fig. 1, IC (104) is accommodated within inner PCB layer (109).....¶[0031], lines 1-4);
wherein the first chip assembly and the second chip assembly are electrically connected with each other (Conductor (110) transmits electrical signals from the MEMS die to the IC.....¶[0028], lines 7-13) and
the printed circuit board is provided with an inlet sound hole through it (Acoustic port (106)),
the printed circuit board is a multilayer structure (The PCB is made of multiple layers, visible in Fig. 1 and detailed in ¶[0031]) comprising
a chip mounting layer (First solder mask layer (112) on which MEMS chip is mounted),
a first alignment layer (Metal layer (114) aligns the embedded circuitry with gaps in layer (112)),
at least one shielding layer (The IC (104) is embedded in inner PCB layer (109), which may be constructed out of FR-4 laminate (laminate indicating a plurality of layers), with the layer (potentially layers, depending on laminate thickness) of laminate laterally adjacent to IC (104) shielding IC (104) from the environment.....¶[0031], lines 1-5)
a second alignment layer (Metal layer (115) aligns the embedded circuitry with gaps in layer (113)),
and an SMT layer (Second solder mask layer (113) provides a surface layer for mounting the PCB with other components) arranged in sequence from one side close to the first chip assembly to the other side away from the first chip assembly (Visible in Fig. 1),
the chip mounting layer, the first alignment layer, the second alignment layer, and the SMT layer are electrically coupled to each other (Shown in Fig. 1, Via (130) couples all metal and solder layers together.....¶[0031], lines 7-10),
the second chip assembly is electrically connected with the first alignment layer (¶[0031], lines 5-7),
wherein the shielding layer is provided with an avoiding aperture running through it, forming an avoiding cavity (The at least one shielding layer is open (with an aperture) at least wherein IC (104) is placed, such aperture forming a cavity (avoiding) cavity for accommodating IC (104)).
Vos fails to explicitly teach a plurality of shielding layers, and therefore also fails to explicitly teach details regarding the plurality of shielding layers.
Harada teaches a printed circuit board comprised of a plurality of shielding layers (Shown in Fig. 2, active component (2)) is enclosed (shielded) on the sides by a plurality of layers (starting with the layer indicated by symbol (14) and the two layers below it),
wherein each of the plurality of shielding layers is connected with a grounding point of the printed circuit board (The vias (12) of each layer (including shielding layers) are connected to ground lines of the PCB…..Col. 9, lines 23-24) and provided with an avoiding aperture running through it (Each shielding layer has a through hole (avoiding aperture) (14)…..Col. 4, lines 63-64),
all of the avoiding apertures of the plurality of shielding layers collectively form an avoiding cavity (The stacked holes form a cavity for active component (2) to be accommodated within…..Col. 4, lines 63-64),
a chip assembly (Active component (2), analogous to the second chip assembly of Vos) is accommodated in the avoiding cavity (The stacked holes form a cavity for active component (2) to be accommodated within…..Col. 4, lines 63-64).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vos by Harada to provide the benefit of wherein internal board impedances may be easily calculated, simplifying circuit design (Harada, Col. 7, lines 56-18). Such modification would make obvious the feature(s) wherein the multilayer structure comprises a plurality of shielding layers, and each of the plurality of shielding layers is connected with a grounding point of the printed circuit board and provided with an avoiding aperture running through it, all of the avoiding apertures of the plurality of shielding layers collectively form an avoiding cavity, the second chip assembly is accommodated in the avoiding cavity.
Regarding claim 3, the combination of Vos and Harada teach the microphone as described in claim 1.
Vos additionally teaches wherein the printed circuit board comprises a first conductive pillar which electrically connected with the second chip assembly, the first alignment layer, and the chip mounting layer in sequence (Shown in Fig. 1, a pillar extends up from the left side of IC (104), connecting it to first alignment layer (114) and chip mounting layer (112)).
Regarding claim 4, the combination of Vos and Harada teach the microphone as described in claim 3.
Vos additionally teaches wherein the printed circuit board further comprises a second conductive pillar (Shown in Fig. 1, Via (130) is a conductive pillar structure couples all mounting and alignment layers together.....¶[0031], lines 7-10) which electrically connected with the chip mounting layer, the first alignment layer, the second alignment layer, and the SMT layer (¶[0031], lines 7-10), the avoiding aperture is used for avoiding the second conductive pillar (Shown in Fig. 1, the via (130) is distanced from and therefore avoids embedded circuit (104), provided to the cavity of inner PCB layer (109)).
Regarding claim 8, the combination of Vos and Harada teach the microphone as described in claim 3.
Vos additionally teaches wherein FR4 is filled between two adjacent structures of the multiple structure of the printed circuit board (Inner PCB layer (109) is shown in Fig. 1 as located between the alignment layers (114, 115) and the ASIC (104) (which would be encompassed by shielding layers as modified by Harada) and is made of multiple layers of FR-4, at least one of which would be positioned between the shielding layers and the alignment layers.....¶[0031], lines 1-5).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Vos in view of Harada in further view of Hong et al (hereinafter Hong), US-PG-PUB No. 2012/0087097.
Regarding claim 2, the combination of Vos and Harada teach the microphone as described in claim 1.
Vos additionally teaches wherein each of the chip mounting layer, the first alignment layer, the second alignment layer, and the SMT layer is a metal layer (¶[0031], lines 1-3).
This further combination fails to teach wherein the plurality of shielding layers are metal layers.
Hong teaches a PCB with embedded components (Shown in Fig. 1, PCB with embedded component (200).....¶[0036], lines 1-4) wherein a shielding layer (Grounded metal core layer (100) is provided with a cavity for the component, and is therefore analogous to the plurality of shielding layers of Harada.....¶[0017], lines 1-6) is a metal layer (It is a metal core)).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vos and Harada by Hong to provide the benefit of improved heat radiation efficiency of embedded devices (Hong, ¶[0016], lines 1-5). Such modification would make obvious the feature(s) wherein the plurality of shielding layers are metal layers.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Vos in view of Harada in further view of Hsu et al (hereinafter Hsu), US-PG-PUB No. 2025/0206600.
Regarding claim 5, the combination of Vos and Harada teach the microphone as described in claim 1.
Vos additionally teaches wherein the first chip assembly comprises a first MEMS chip fixed with the printed circuit board (Shown in Fig. 1, MEMS die (102) is fixed to PCB (180)).
This further combination fails to teach a second MEMS chip.
Hsu teaches a MEMS microphone wherein a first chip assembly comprises a first MEMS chip and a second MEMS chip spaced apart from the first MEMS chip (Shown in Fig. 2, and described in ¶[0038], first and second MEMS devices (205, 207)), the first MEMS chip and the second MEMS chip are fixed with a printed circuit board (MEMS devices are affixed to PCB (250)).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vos and Harada by Hsu to provide the benefit of multiple pick-up patterns for the microphone device (Hsu, ¶[0006], lines 8-17). Such modification would make obvious the feature(s) wherein a first chip assembly comprises a first MEMS chip and a second MEMS chip spaced apart from the first MEMS chip, the first MEMS chip and the second MEMS chip are fixed with the printed circuit board.
Regarding claim 6, the combination of Vos, Harada, and Hsu teach the microphone as described in claim 5.
Hsu additionally teaches wherein a second chip assembly comprises a first ASIC chip and a second ASIC chip spaced apart from the first ASIC chip (Shown in Fig. 2, ASICs (270, 280)), the first ASIC chip is electrically connected with the first MEMS chip, the second ASIC chip is electrically connected with the second MEMS chip (Visible in Fig. 2, each ASIC is paired with one of the MEMS devices).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vos, Harada, and Hsu further by Hsu to provide the benefit of multiple pick-up patterns for the microphone device (Hsu, ¶[0006], lines 8-17). Such modification would make obvious the feature(s) wherein the second chip assembly comprises a first ASIC chip and a second ASIC chip spaced apart from the first ASIC chip, the first ASIC chip is electrically connected with the first MEMS chip, the second ASIC chip is electrically connected with the second MEMS chip.
Regarding claim 7, the combination of Vos, Harada, and Hsu teach the microphone as described in claim 6.
Hsu additionally teaches wherein the first ASIC chip is electrically connected to the first MEMS chip via a first bond wire (Shown in Fig. 2 and described in ¶[0042], first bond wire (274)), and the second ASIC chip is electrically connected to the second MEMS chip via a second bond wire (284).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vos, Harada, and Hsu further by Hsu to provide the benefit of multiple pick-up patterns for the microphone device (Hsu, ¶[0006], lines 8-17). Such modification would make obvious the feature(s) wherein the first ASIC chip is electrically connected to the first MEMS chip via a first bond wire, and the second ASIC chip is electrically connected to the second MEMS chip via a second bond wire.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wickstrom, US-PG-PUB No. 2013/0156235 and Cheng et al, US-PG-PUB No. 2022/0289556 both teach arrangements for multiple MEMS devices in a MEMS microphone.
Chua, US Patent No. 6,388,205 teaches a printed circuit board with multiple shielding layers for cavities and circuitry traces.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN RINEHART whose telephone number is (571)272-2778. The examiner can normally be reached M-F 10:00 AM - 6:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahmad Matar can be reached on (571) 272-7488. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN RINEHART/Examiner, Art Unit 2694
/ALEXANDER KRZYSTAN/Primary Examiner, Art Unit 2694
