DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 8-10, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. US 2022/0199330 A1 (hereafter referred to as Kwon) in view of Cha et al. US 2023/0141461 A1 (hereafter referred to as Cha).
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Figure 1: Examiner annotated Fig. 6 of Kwon showing a first main surface (Z1) a second main surface (Z2) a first side surface (Y1) and a second side surface (Y2).
Regarding claim 1, Kwon discloses
A multilayer ceramic capacitor that has a dimension in a first direction (Z) along a first axis (Z) equal to or greater than 1.5 times a dimension in a second direction (Y) along a second axis (Y) orthogonal to the first axis (Abstract, para. [0036]), and is configured to be mounted on a mounting surface (200 – Fig. 7) perpendicular to the first axis (para. [0040]), the multilayer ceramic capacitor comprising: a ceramic body (110 – Fig. 7 para. [0071]) having: a pair of main surfaces perpendicular to the first axis (Z1, Z2 – present office action figure 1 (hereafter called POA1)), a pair of side surfaces perpendicular to the second axis (Y1, Y2 – POA1), an end surface perpendicular to a third axis orthogonal to the first axis and the second axis (S1, S2 – Fig. 4), a multilayer body (130 – Fig. 4 para. [0030]) including a plurality of internal electrodes (121, 122 – Fig. 6 para. [0030]) that are stacked in the second direction and are led out to a connection end on the end surface (Fig. 3 para. [0030]), and a pair of margin portions (141, 142 – Fig. 2) that cover the multilayer body from respective sides in the first direction (para. [0030]), and have a grain growth inhibiting element (para. [0062]); and an external electrode covering the end surface (131, 132 – Fig. 1 para. [0030]). Kwon fails to explicitly disclose wherein a pair of margin portions have a higher concentration of a grain growth inhibiting element than the multilayer body.
Cha discloses wherein a pair of margin portions have a higher concentration of a grain growth inhibiting element than the multilayer body (para. [0007] and Table 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a higher content of the growth inhibiting element Mg as taught by Cha in the margin portions of Kwon to improve moisture resistance (para. [0043] of Cha).
Regarding claim 2, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 1, wherein the grain growth inhibiting element is at least one of the following elements: Mg, Mn, and a rare earth element (para. [0062] of Kwon).
Regarding claim 8, Kwon as modified by Cha discloses
A circuit board comprising: the multilayer ceramic capacitor according to claim 1 (100 – Fig. 7 para. [0071] of Kwon); and a mounting substrate (201 – Fig. 7 para. [0072] of Kwon) having a mounting surface perpendicular to the first axis (top of 201 – Fig. 7 para. [0071-0072] of Kwon), and a connection electrode (210, 220 - Fig. 7 para. [0070] of Kwon) that is provided on the mounting surface and connected to the external electrode of the multilayer ceramic capacitor through solder (Fig. 7 para. [0071] of Kwon).
Regarding claim 9, Kwon discloses
A multilayer ceramic capacitor that has a dimension in a first direction (Z) along a first axis (Z) equal to or greater than 1.3 times a dimension in a second direction (Y) along a second axis (Y) orthogonal to the first axis (Abstract, para. [0036]), and is configured to be mounted on a mounting surface (200 – Fig. 7) perpendicular to the first axis (para. [0040]), the multilayer ceramic capacitor comprising: a ceramic body (110 – Fig. 7 para. [0071]) having: a pair of main surfaces perpendicular to the first axis (Z1, Z2 – POA1) a pair of side surfaces perpendicular to the second axis (Y1, Y2 – POA1), an end surface perpendicular to a third axis orthogonal to the first axis and the second axis (S1, S2 – Fig. 4), a multilayer body (130 – Fig. 4 para. [0030]) including a plurality of internal electrodes (121, 122 – Fig. 6 para. [0030]) that are stacked in the second direction and are led out to a connection end on the end surface (Fig. 3 para. [0030]), and a pair of margin portions (141, 142 – Fig. 2) that cover the multilayer body from respective sides in the first direction (para. [0030]), and have a grain growth inhibiting element (para. [0062]); and an external electrode covering the end surface (131, 132 – Fig. 1 para. [0030]). Kwon fails to explicitly disclose wherein a pair of margin portions have a higher concentration of a grain growth inhibiting element than the multilayer body.
Cha discloses wherein a pair of margin portions have a higher concentration of a grain growth inhibiting element than the multilayer body (para. [0007] and Table 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a higher content of the growth inhibiting element Mg as taught by Cha in the margin portions of Kwon to improve moisture resistance (para. [0043] of Cha).
Regarding claim 10, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 9, wherein the grain growth inhibiting element is at least one of the following elements: Mg, Mn, and a rare earth element (para. [0062] of Kwon).
Regarding claim 16, Kwon as modified by Cha discloses
A circuit board comprising: the multilayer ceramic capacitor according to claim 9 (100 – Fig. 7 para. [0071]); and a mounting substrate (201 – Fig. 7 para. [0072]) having a mounting surface perpendicular to the first axis (top of 201 – Fig. 7 para. [0071-0072]), and a connection electrode (210, 220 - Fig. 7 para. [0070]) that is provided on the mounting surface and connected to the external electrode of the multilayer ceramic capacitor through solder (Fig. 7 para. [0071]).
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cha and further in view of Yamazaki US 2005/0264975 A1 (hereafter referred to as Yamazaki).
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Figure 2: Examiner annotated Fig. 9 of Yamazaki pointing out the lamination direction. The top-bottom portion of Yamazaki corresponds to the left-right portions of Kwon in reference to the lamination direction.
Regarding claim 3, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 1. Kwon fails to disclose wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body.
Cha fails to disclose fails to disclose wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body.
Yamazaki discloses wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body (present office action figure 2 (hereafter called POA2) shows the pair of main surfaces (left-right of POA2) are flatter than the pair of side surfaces (surfaces in the lamination direction or top-bottom of POA2), which are curved. Abstract and paras. [0021], [0050-0061]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the side surfaces (opposing surfaces in the lamination direction) of Kwon curved (and hence less flat than the main surfaces) as taught by Yamazaki to increase breaking strength of the multilayer ceramic component and prevent chipping (paras. [0052], [0094-0095] and Table 2 of Yamazaki).
Regarding claim 11, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 9. Kwon fails to disclose wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body.
Cha fails to disclose fails to disclose wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body.
Yamazaki discloses wherein the pair of main surfaces have higher flatness than the pair of side surfaces in the ceramic body (POA2 shows the pair of side surfaces (left-right of POA2) are flatter than the pair of side surfaces (surfaces in the lamination direction or top-bottom of POA2) which are curved. Abstract and paras. [0021], [0050-0061]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the side surfaces (opposing surfaces in the lamination direction) of Kwon curved (and hence less flat than the main surfaces) as taught by Yamazaki to increase breaking strength of the multilayer ceramic component and prevent chipping (paras. [0052], [0094-0095] and Table 2 of Yamazaki).
Claim(s) 4-5 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cha and further in view of Lee et al US 2013/0107422 A1 (hereafter referred to as Lee).
Regarding claim 4, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 1. Kwon fails to disclose wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis.
Cha fails to disclose wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis.
Lee discloses wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis (133 – Fig. 5 paras. [0014]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the connection portion of the internal electrode less wide than the central portion to prevent impurities (such as moisture) from entering the internal electrodes and preventing short-circuits (para. [0072] of Lee).
Regarding claim 5, Kwon as modified by Cha and further modified by Lee discloses
The multilayer ceramic capacitor according to claim 4, wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction. Kwon fails to disclose wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction.
Cha fails to disclose wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction.
Lee discloses wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction (Table 2). More specifically, Lee discloses an optimum range of greater than 80% of and equal to or less than 85% of a dimension in the first direction of the central portion in the third direction to best reduce contact generation frequency and minimize defective contact and crack generation due to infiltration of plating solution (paras. [0106-0107]). Furthermore, Table 2 shows that the contact area ratio is a result effective variable for contact frequency generation.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have the ratio of a dimension of the connection end in the first direction is equal to or greater than 60% (more preferably 80%) of and equal to or less than 90% (more preferably 85%) as taught by Lee to prevent defective contact, prevent infiltration of impurities and prevent degradation of insulation resistance in the multilayer electronic component of modified Kwon. Furthermore, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 12, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 9. Kwon fails to disclose wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis.
Cha fails to disclose wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis.
Lee discloses wherein the plurality of internal electrodes have larger distances from the pair of main surfaces at the connection end than in a central portion in a third direction along the third axis (133 – Fig. 5 paras. [0014]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the connection portion of the internal electrode less wide than the central portion to prevent impurities (such as moisture) from entering the internal electrodes and preventing short-circuits (para. [0072] of Lee).
Regarding claim 13, Kwon as modified by Cha and further modified by Lee discloses
The multilayer ceramic capacitor according to claim 12, wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction. Kwon fails to disclose wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction.
Cha fails to disclose wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction.
Lee discloses wherein, in the plurality of internal electrodes, a dimension of the connection end in the first direction is equal to or greater than 60% of and equal to or less than 90% of a dimension in the first direction of the central portion in the third direction (Table 2). More specifically, Lee discloses an optimum range of greater than 80% of and equal to or less than 85% of a dimension in the first direction of the central portion in the third direction to best reduce contact generation frequency and minimize defective contact and crack generation due to infiltration of plating solution (paras. [0106-0107]). Furthermore, Table 2 shows that the contact area ratio is a result effective variable for contact frequency generation.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have the ratio of a dimension of the connection end in the first direction is equal to or greater than 60% (more preferably 80%)of and equal to or less than 90% (more preferably 85%) as taught by Lee to prevent defective contact, prevent infiltration of impurities and prevent degradation of insulation resistance in the multilayer electronic component of Kwon. Furthermore, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cha, in view of Lee, and further in view of Shibasaki et al. US 2020/0234886 A1 (hereafter referred to as Shibasaki).
Regarding claim 6, Kwon as modified by Cha and Lee discloses
The multilayer ceramic capacitor according to claim 4. Kwon fails to explicitly disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Cha fails to disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Lee fails to disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Shibasaki discloses wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction (Figs. 4-9 (note that Mn is an example and may instead be Mg or a rare earth element); Abstract and paras. [0011] and [0013]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a substantially constant concentration of Mg in a section where the connection end is present in the first direction (and in particular an active portion where electrostriction occurs) as taught by Shibasaki to suppress the growth of coarse crystal grains, thereby mitigating cracks being generated by electrostriction (para. [0014] of Shibasaki).
Regarding claim 14, Kwon as modified by Cha and Lee discloses
The multilayer ceramic capacitor according to claim 12. Kwon fails to explicitly disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Cha fails to disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Lee fails to disclose wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction.
Shibasaki discloses wherein in the multilayer body, the concentration of the grain growth inhibiting element is substantially constant in a section where the connection end is present in the first direction (Figs. 4-9 (note that Mn is an example and may instead be Mg or a rare earth element); Abstract and paras. [0011] and [0013]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a substantially constant concentration of Mg in a section where the connection end is present in the first direction (and in particular an active portion where electrostriction occurs) as taught by Shibasaki to suppress the growth of coarse crystal grains, thereby mitigating cracks being generated by electrostriction (para. [0014] of Shibasaki).
Claim(s) 7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Cha and further in view of Teraoka US 2016/0227650 A1 (hereafter referred to as Teraoka).
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Figure 3: Examiner annotated Fig. 9B of Teraoka pointing out a sealing surface.
Regarding claim 7, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 1. Kwon fails to disclose a package comprising: the multilayer ceramic capacitor according to claim 1; a carrier tape having a sealing surface perpendicular to the first axis and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess.
Cha fails to disclose a package comprising: the multilayer ceramic capacitor according to claim 1; a carrier tape having a sealing surface perpendicular to the first axis and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess.
Teraoka discloses A package (Figs. 9A and 9B) comprising: a multilayer ceramic capacitor (100); a carrier tape (60 – Fig. 9B para. [0094]) having a sealing surface (sealing surface – present office action figure 3 (hereafter called POA3)) perpendicular to the first axis and a recess (60a – Figs. 9A and 9B para. [0094-0095]) that is recessed from the sealing surface in the first direction (first direction – POA3) and accommodates the multilayer ceramic capacitor; and a top tape (61 – Fig. 9B para. [0094]) that is attached to the sealing surface and covers the recess (POA3).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the multilayer ceramic capacitor of Kwon as modified by Cha in a package, wherein the package comprises a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess in order to package the device for transportation and create reals for pick-and-place machines, as well as protecting the multilayer ceramic capacitors from contaminants while in storage.
Regarding claim 15, Kwon as modified by Cha discloses
The multilayer ceramic capacitor according to claim 9. Kwon fails to disclose a package comprising: the multilayer ceramic capacitor according to claim 9; a carrier tape having a sealing surface perpendicular to the first axis and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess.
Cha fails to disclose a package comprising: the multilayer ceramic capacitor according to claim 9; a carrier tape having a sealing surface perpendicular to the first axis and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess.
Teraoka discloses A package (Figs. 9A and 9B) comprising: a multilayer ceramic capacitor (100); a carrier tape (60 – Fig. 9B para. [0094]) having a sealing surface (sealing surface – POA3) perpendicular to the first axis and a recess (60a – Figs. 9A and 9B para. [0094-0095]) that is recessed from the sealing surface in the first direction (first direction – POA3) and accommodates the multilayer ceramic capacitor; and a top tape (61 – Fig. 9B para. [0094]) that is attached to the sealing surface and covers the recess (POA3).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the multilayer ceramic capacitor of Kwon as modified by Cha in a package, wherein the package comprises a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess in order to package the device for transportation and create reals for pick-and-place machines, as well as protecting the multilayer ceramic capacitors from contaminants.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130141837 A1: Fig. 2B; internal electrode shape
US 20140307362 A1: Figs. 3-4; capacitor with T/W > 1.0 an internal electrode perpendicular to mounting surface
US 20140311783 A1: Figs. 3-4; capacitor with T/W > 1.0 an internal electrode perpendicular to mounting surface
US 20170076867 A1: Figs. 2D & 2E; non-flat side margin portions
JP 2010050263 A: More Mg contained in protective layer than multilayer body
US 20200194176 A1: Mg contained in different amounts in different portions of the side margin. Side margin doesn’t explicitly contain more Mg than multilayer body
US 20080304204 A1: Mg content of side margin and body
US 20190180936 A1: Mn content greater in margin portions covering ends of internal electrodes (paras. [0085-0087], [0090-0091] and Table 1)
US 20140334062 A1: side surfaces have a step portion
US 20120229949 A1: curved side portions
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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