Prosecution Insights
Last updated: August 18, 2026
Application No. 19/007,851

NOISE LEARNING OF MEASUREMENTS WITH KNOWN STATE INITIALIZATION

Non-Final OA §102§Other
Filed
Jan 02, 2025
Examiner
BARNETT, JACK KENSINGTON
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
19 granted / 23 resolved
+27.6% vs TC avg
Strong +19% interview lift
Without
With
+18.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
11 currently pending
Career history
40
Total Applications
across all art units

Statute-Specific Performance

§101
7.6%
-32.4% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 23 resolved cases

Office Action

§102 §Other
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 12, and 19 are rejected under 35 U.S.C. 102a1 as being anticipated by Lin (“Independent state and measurement characterization for quantum computers”). Regarding claim 1, Lin teaches: A system, comprising: a memory that stores computer executable components; and a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise: (While not explicitly discussed by Lin, these limitations are considered by the examiner to be routine and exceptionally well known in the art.) an initialization component that initializes a qubit with a known state to obtain state preparation errors of the qubit; (see pg. 4, LHC, para. 2: Protocols that estimate gate error strengths independently of SPAM offer a solution to the problem. Here we utilize the recently proposed cycle benchmarking (CB) [25] procedure. CB estimates the process infidelity of a composite cycle (consisting of a round of the original gates ˜G composed with a round of “dressing” gates ˜D), averaged over all Pauli dressing gates, namely rCB.) It is well known in the art that cycle benchmarking initializes a qubit in (a known) ground state, to obtain process fidelity and SPAM (state preparation and measurement) errors. a measurement component that measures properties of the known state of the qubit; (see pg. 4, LHC, para. 2: Protocols that estimate gate error strengths independently of SPAM offer a solution to the problem. Here we utilize the recently proposed cycle benchmarking (CB) [25] procedure. CB estimates the process infidelity of a composite cycle (consisting of a round of the original gates ˜G composed with a round of “dressing” gates ˜D), averaged over all Pauli dressing gates, namely rCB. And see pg. 4, LHC, para. 5: We will show in Appendix B that βic P,t can be bounded using the measured βP,t and rCB(˜UP,UP).) It is well known in the art that cycle benchmarking measures properties of the qubit state to calculate process infidelity and SPAM errors. and an execution component that performs, on a quantum system, cycle benchmarking for measurements on the qubit within a quantum circuit to obtain, by using the properties of the known state, a noise model of the measurements that determines state errors of the qubit from the state preparation errors. (see pg. 4, LHC, para. 2: Protocols that estimate gate error strengths independently of SPAM offer a solution to the problem. Here we utilize the recently proposed cycle benchmarking (CB) [25] procedure. CB estimates the process infidelity of a composite cycle (consisting of a round of the original gates ˜G composed with a round of “dressing” gates ˜D), averaged over all Pauli dressing gates, namely rCB. And see pg. 5, LHC, table 1: Upper and lower bounds for one-qubit SPAM error rates [Eq. (12)] on a target qubit qt. α and β are defined in Eq.(10). rt,a is short hand for rCB( ˜Ct,a,Ct,a). Also see that the bounds of state preparation and measurement errors are determined based on rt,a (shorthand for rCB, calculated via cycle benchmarking). The bounds of SP and M are considered to be a noise model that determines state errors (measurement errors) from state preparation errors. Claims 12 and 19 correspond to claim 1, and are similarly rejected. Allowable Subject Matter Claims 2, 13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. At least by their dependency on one of claims 2, 13, or 20, claims 3-11 and 14-18 are similarly objected to. The following is a statement of reasons for the indication of allowable subject matter: the elements of claims 2, 13, and 20 were neither found through search of the prior art, nor considered to be obvious by the examiner. In particular the prior art of record does not teach or suggest, in combination with the remaining limitations and in the context of their claims as a whole the concept of determining state errors (considered to be the measurement errors of SPAM errors) from state preparation errors using the measured thermal population of a first excited state of the qubit as required by claims 2, 13, and 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Erhard, “Characterizing large-scale quantum computers via cycle benchmarking” explicitly describes how and why cycle benchmarking is performed. Laflamme, “Algorithmic cooling for resolving state preparation and measurement errors in quantum computing” describes a method for separating state preparation from measurement errors that touches on thermal population. However, instead of using a measured thermal population to separate the SP and M errors as suggested in the instant application, they cool the qubit, effectively reducing the thermal population to 0 to set up an ideal state initialization. This eliminates the SP error, meaning the M error can be isolated and determined. Then they can repeat the experiment without ideal state initialization to calculate total SPAM error, allowing the SP error to be inferred from knowing the M error and total SPAM error. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK KENSINGTON BARNETT/Examiner, Art Unit 2111 /MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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Prosecution Timeline

Jan 02, 2025
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §102, §Other (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+18.9%)
2y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 23 resolved cases by this examiner. Grant probability derived from career allowance rate.

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