Prosecution Insights
Last updated: August 16, 2026
Application No. 19/007,874

CAPACITOR ELEMENT

Non-Final OA §102
Filed
Jan 02, 2025
Priority
Jun 16, 2023 — JP 2023-099240 +1 more
Examiner
MCFADDEN, MICHAEL P
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
725 granted / 840 resolved
+26.3% vs TC avg
Strong +20% interview lift
Without
With
+19.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
31 currently pending
Career history
849
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
4.7%
-35.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 840 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Claim(s) 1 and 15-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by OTANI (US 2024/0332346). Regarding claim 1, OTANI discloses a capacitor element (Fig. 1-10), comprising: a capacitor portion (Fig. 6, C) including: an anode plate (Fig. 6, 51A) including a core portion (Fig. 6, 52A) and a porous portion (Fig. 6, 54A) at at least one main surface of the core portion (Fig. 6), a dielectric layer (dielectric layer [0111]) at a surface of the porous portion (Fig. 6 [0111]), and a cathode layer (Fig. 6, 56A) at a surface of the dielectric layer (Fig. 6 [0111]); a seal layer (Fig. 6, 81) covering the capacitor portion (Fig. 6); a first through-hole conductor (Fig. 6, 12A) extending through the capacitor portion and the seal layer in a thickness direction and electrically directly connected to the anode plate (Fig. 6), and having two end portions (Fig. 6, 12A on 81 at top and bottom) drawn out to a surface of the seal layer (Fig. 6); a second through-hole conductor (Fig. 7, 12B) extending through the capacitor portion and the seal layer in the thickness direction and electrically directly connected to the cathode layer (Fig. 7), and having two end portions (Fig. 7, 12B on top and bottom of 81) drawn out to the surface of the seal layer (Fig. 7); a first outer electrode layer (Fig. 6, 13Aa) at the surface of the seal layer and electrically connected to the first through-hole conductor (Fig. 6), wherein at least a part of the first outer electrode layer overlaps the cathode layer in the thickness direction (Fig. 6-7); and a second outer electrode layer (Fig. 7, 13Ba) at a surface of the seal layer and electrically connected to the second through-hole conductor (Fig. 7). Regarding claim 15, OTANI further discloses: an inner via conductor (Fig. 7, 82) extending through the seal layer in the thickness direction (Fig. 7), the inner via conductor having a first end portion thereof electrically connected to the second outer electrode layer and a second end portion thereof electrically connected to the cathode layer (Fig. 7). Regarding claim 16, OTANI further discloses that the cathode layer includes: a solid electrolyte layer (Fig. 7, 56Aa) on a surface of the dielectric layer ([0111]), a first conductor layer (Fig. 7, 56Ab CRL [0118]) on a surface of the solid electrolyte layer (Fig. 7), and a second conductor layer (Fig. 7, 56Ab ML [0118]) on a surface of the first conductor layer and electrically directly connected to the second through-hole conductor (Fig. 7). Allowable Subject Matter Claims 2-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 2-8 and 12-14, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the cathode layer includes a first copper layer, the first outer electrode layer includes a second copper layer, and the second outer electrode layer includes a third copper layer, and wherein d1 ≥ d2 and d1 ≥ d3 where a thickness of the first copper layer of the cathode layer is denoted with d1, a thickness of the second copper layer of the first outer electrode layer is denoted with d2, and a thickness of the third copper layer of the second outer electrode layer is denoted with d3” in combination with the other claim limitations. Regarding claims 9-11, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein S1 > S2 where an area of the first outer electrode layer is denoted with S1, and an area of the second outer electrode layer is denoted with S2” in combination with the other claim limitations. Additional Relevant Prior Art: Nakamura et al (US 2006/0120014) teaches relevant art in Fig. 1-9. Furukawa (US 2020/0312576) teaches relevant art in Fig. 1-30. FERNANDES et al (US 2021/0074629) teaches relevant art in Fig. 1-6. KUSUYAMA et al (US 2023/0120573) teaches relevant art in Fig. 1-13. TAKAHASHI (US 2024/0186071) teaches relevant art in Fig. 1-4. YOSHIKAWA et al (US 2024/0186072) teaches relevant art in Fig. 1-15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jan 02, 2025
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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COMPONENT CONFIGURED WITH INTRINSIC SHIELDING AND PROCESS OF IMPLEMENTING THE SAME
3y 2m to grant Granted Aug 11, 2026
Patent 12706248
MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD FOR PRODUCING MULTILAYER CERAMIC ELECTRONIC COMPONENT
2y 7m to grant Granted Aug 11, 2026
Patent 12706250
MULTILAYER ELECTRONIC COMPONENT
2y 0m to grant Granted Aug 11, 2026
Patent 12695029
MULTILAYER CERAMIC CAPACITOR
2y 7m to grant Granted Jul 28, 2026
Patent 12695030
CERAMIC CAPACITOR
2y 2m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+19.8%)
2y 2m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 840 resolved cases by this examiner. Grant probability derived from career allowance rate.

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