Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1, 5-10 and 14-19
Cancelled: 4 and 13
Added: 27 and 28
Therefore, claims 1-3, 5-12 and 14-28 are currently pending in the instant application.
Response to Arguments
Applicant's arguments filed 03/23/2026 have been fully considered but they are not persuasive. The office has to respectfully disagree with the argument that the prior art does not disclose n sub-current sources for n pixel groups. Although Luo discloses a sub-current source that is connected to all the pixels, however Lee discloses a current source that can be connected to one row of pixels. Therefore, Lee teaches n current sources for n pixel groups. Furthermore, the n current sources can be connected to the same reference current source or individual reference current source as design requirement. The claim does not recite that all n sub-current sources are connected to the same reference current source and n is equal to or greater than 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-9, 19-21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US 2025/0131873 A1, hereinafter “Luo”) in view of Lee et al. (US 2023/0005419 A1, hereinafter “Lee”).
As to claim 1, Luo discloses a display device (Fig. 2) comprising:
a pixel array (33) including n pixel groups (Para. 0117, rows of pixels);
a reference current source (Fig. 7 element 32121) connected to the pixel array (33) and configured to provide a reference current (Para. 0083); and
a sub-current source (32122, 3211) and n pixel circuits (333, each pixel circuit in a row) included in each of the n pixel groups and connected to the reference current source (32121; Para. 0083),
wherein each of the sub-current source (32122) is configured to provide a first mirrored current (second current) that mirrors the reference current (32121; Para. 0083),
wherein each of the n pixel circuits (333) is configured to provide a second mirrored current (First current) that mirrors the first mirrored current (Second current; Para. 0078, 0083-0084), and
wherein n is a natural number (Para. 0117),
wherein the reference current source (32122) comprises a reference transistor (left transistor of the current mirror 32122),
wherein each of the first sub-current source (32122) comprises:
a first transistor (right transistor of the current mirror 32122) connected to the reference transistor (3211) and configured to provide the first mirrored current (second current) that mirrors the reference current (32121); and
a second transistor (3211) connected to one terminal of the first transistor, and configured to provide the first mirrored current (second current),
wherein the n pixel circuits comprise a first pixel circuit (33), and
wherein the first pixel circuit comprises a third transistor (331, for each pixel circuit) connected to the second transistor (3211) and configured to provide the second mirrored current (First current; Para. 0083-0084) that mirrors the first mirrored current (Second current).
Luo does not disclose n sub-current source (Fig. 7 element 32122, 3211) and n pixel circuits (333) included in each of the n pixel groups and connected to the reference current source.
However, Lee (Fig. 6) teaches n sub-current source (127; Para. 0076, “the current supply unit 127 may be provided for every row, and the current supply unit 127 of each row may be shared by a plurality of pixels PXs in the same row”) and n pixel circuits (401 in the same row) included in each of the n pixel groups (Fig. 3; pixel groups of each row) and connected to the reference current source (Fig. 6 element 57; Para. 0130).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee to include a current source for each row in the device disclosed by Luo. The combination would have yielded predictable results of driving the pixel circuits (Lee; Para. 0076).
As to claim 19, Luo discloses a display device (Fig. 2) comprising:
a pixel array (33) including n pixel groups (Para. 0117, each rows of pixels);
a reference current source (Fig. 7 element 32121) connected to the pixel array (33) and configured to provide a reference current (Para. 0083); and
a sub-current source (3211, 32122) each disposed in a corresponding one of the n pixel groups (33) and connected to the reference current source (32121; Para. 0083),
wherein each of the sub-current sources includes:
a first transistor (32122, right transistor) that forms a first current mirror with a reference transistor (32122, left transistor) of the reference current source (32121), and
wherein each of the sub-current sources and each of the n pixel circuits (33) includes a second current mirror (3211, 331; Para. 0112) connected to the first transistor (32122, right transistor).
Luo does not expressly disclose n sub-current sources each disposed in a corresponding one of the n pixel groups and connected to the reference current source, and
n pixel circuits included in each of the n pixel groups and connected to the sub-current sources.
However, Lee (Fig. 6) teaches n sub-current sources (127) each disposed in a corresponding one of the n pixel groups (each row of pixels) and connected to the reference current source (57; Para. 0076, 0130),
n pixel circuits (401) included in each of the n pixel groups (rows of pixels) and connected to the sub-current sources (127).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee to include a current source for each row in the device disclosed by Luo. The combination would have yielded predictable results of driving the pixel circuits (Lee; Para. 0076).
As to claim 20, Luo (Fig. 7) discloses the display device of claim 19, wherein the second current mirror (3211, 331) includes: a second transistor (3211) connected to one terminal of the first transistor (32122, right transistor); and
a plurality of third transistors (331, fig. 9) connected to the second transistor (3211).
As to claim 2, Luo (Fig. 10) discloses the display device of claim 1, wherein:
each of the n pixel groups includes a plurality of light-emitting elements (3331, pixels in a row), and
the plurality of light-emitting elements (3331) in each of the n pixel groups are connected to each of the n pixel circuits (33).
As to claim 3, Luo (Fig. 11) discloses the display device of claim 2, wherein the second mirrored current (first current) is configured to be provided to each of the plurality of light-emitting elements (3331).
As to claim 5, Luo (Fig. 15) discloses the display device of claim 1, wherein a first pixel group of the n pixel groups comprises a light-emitting element (3331), connected to the third transistor (Fig. 9 element 331) and configured to receive the second mirrored current (First current).
The above rejection also stands for the similar device of claim 21.
As to claim 8, Luo (Fig. 8) discloses the display device of claim 1, wherein:
the first transistor (32122) is an NMOS transistor, and
the second transistor (3211) and the plurality of third transistors (331) are PMOS transistors (Para. 0077).
The above rejection also stands for the similar device of claim 23.
As to claim 9, Luo (Fig. 7) discloses the display device of claim 1, wherein:
the first transistor (32122) is a PMOS transistor (Para. 0110), and
the second transistor (3211) and the plurality of third transistors (331) are NMOS transistors (Para. 0076).
The above rejection also stands for the similar device of claim 24.
As to claim 25, Luo (Fig. 7) discloses the display device of claim 19, wherein:
the first mirrored current (Second current), mirrored from the reference current (32121) by the first current mirror (32122), is configured to be provided to the first transistor (32122, right transistor) and the second current mirror (3211, 331), and
the second mirrored current (First current), mirrored from the first mirrored current (Second current) by the second current mirror (3211, 321), is configured to be generated (Para. 0083, 0110).
As to claim 26, Luo (Fig. 13) discloses the display device of claim 25, wherein:
each of the n pixel groups includes a plurality of light-emitting elements (3331),
the plurality of light-emitting elements in each of the n pixel groups are connected to the second current mirror (321; Fig. 7), and
the second mirrored current (First current) is configured to be provided to the plurality of light- emitting elements (3331).
Claim(s) 6-7 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Luo and Lee as applied to claims 4 and 20 above, and further in view of Oikawa (US 2002/0135424 A1, hereinafter “Oikawa”).
As to claim 6, Luo (Fig. 9) discloses the display device of claim 1, wherein:
the second transistor (3211) includes a plurality of second sub-transistors connected in series (Para. 0084), and
wherein the third transistor (331) includes a plurality of third sub- transistors connected in series (Para. 0084).
Luo does not disclose the first transistor (32122) includes a plurality of first sub-transistors connected in series.
However, Oikawa (Fig. 2) teaches the first transistor (33) includes a plurality of first sub-transistors connected in series Q31, Q32; Para. 0051).
It would have been obvious to one of ordinary skill in the art to simple substitute the cascaded current mirror of Oikawa for the current mirror of Luo. The substitution would have yielded predictable results of providing the constant current (Oikawa; Para. 0050).
The above rejection also stands for the similar device of claim 22.
As to claim 7, Luo (Fig. 13) discloses the display device of claim 6, wherein:
a first pixel group (33) of the n pixel groups comprises light-emitting element (3331), connected to the third transistor (331) and configured to receive the second mirrored current (First current), and
wherein the light-emitting element is connected to the third sub-transistors (Fig. 9 element 331) and configured to receive the second mirrored current (First current).
Allowable Subject Matter
Claims 10-18 are allowed.
The prior art does not disclose a limitation “a reference current source connected to each of the first sub-current source and the second sub-current source and configured to provide a reference current” when combined with other limitations of the claim.
Claims 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Yang (US 2004/0217934 A1) discloses a second current mirror (Fig. 5).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/Examiner, Art Unit 2625
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