DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/27/2025 and 08/01/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 7-11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu Chinese Patent Document CN 112217185 A and further in view of Wang et al. U.S. Patent Application 2013/0009253 (hereinafter “Wang”).
Regarding claim 1, Xu teaches an input/output (I/O) interface (i.e. electrostatic protection circuit 100)(fig.1), comprising: an I/O terminal (i.e. IN)(fig.1); and a gate component (i.e. transistor MN3 and control module 14)(fig.1), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor MN3)(fig.1), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Xu does not teach an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the input/output (I/O) interface of Xu to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch.
Regarding claim 2, Xu and Wang teach the I/O interface according to claim 1, wherein the input end of the first switch component is directly connected to the I/O terminal (implicit)(Refer to Xu fig.1).
Regarding clam 3, Xu and Wang teach the I/O interface according to claim 2, wherein the first switch component comprises a metal oxide semiconductor (MOS) transistor (i.e. Xu transistor MN3)(fig.1)(i.e. Wang MOSFET 102)(fig.1), and the input end of the first switch component comprises a source electrode or a drain electrode of the MOS transistor (implicit)(refer to Xu transistor MN3)(fig.1).
Regarding claim 4, Xu and Wang teach the I/O interface according to claim 1, wherein the anti-electrostatic discharge apparatus comprises a second switch component (i.e. Wang diode-connected MOSFET 110)(fig.1), and an output end of the second switch component is connected to a gate electrode of the first switch component (implicit)(refer to Wang fig.1).
Regarding claim 5, Xu and Wang teach the I/O interface according to claim 4, wherein the gate component further comprises a phase inverter (i.e. Xu first inverter CV1)(fig.2) connected to an input end of the second switch component (implicit)(refer to Wang gate)(fig.1).
Regarding claim 7, Xu and Wang teach the I/O interface according to claim 4, wherein the first switch component and the second switch component each comprise a metal oxide semiconductor field-efficient transistor (MOS FET) (refer to Wang diode-connected MOSFET 110 and MOSFET 102)(fig.1)(refer also to Xu transistor MN3)(fig.1).
Regarding claim 8, Xu and Wang teach the I/O interface according to claim 4, wherein the second switch component comprises a MOS transistor (implicit)(refer to Wang diode-connected MOSFET 110)(fig.1), and the output end comprises a source electrode or a drain electrode of the MOS transistor (implicit)(refer to Wang fig.1).
Regarding claim 9, Xu and Wang teach the I/O interface according to claim 1, further comprising: a positive terminal (i.e. Xu VDD)(fig.1; a ground terminal (i.e. Xu VSS)(fig.1); and a discharge bridge (i.e. Xu electrostatic bypass 11 and 12)(fig.1) connected between the positive terminal and the ground terminal (implicit); however they do not teach the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the input/output (I/O) interface of Xu and Wang to include the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge to provide the advantage of ensuring proper operation of the circuit.
Regarding claim 10, Xu and Wang teach the I/O interface according to claim 9, wherein the discharge bridge comprises a first unilateral conductive element (i.e. Xu transistor MP1)(fig.1) connected between the I/O terminal and the positive terminal (implicit) and a second unilateral conductive element (i.e. Xu transistor MN1)(fig.1) connected between the I/O terminal and the ground terminal (implicit), wherein the first unilateral conductive element is configured to allow a current to flow only from the I/O terminal to the positive terminal (implicit), and the second unilateral conductive element is configured to allow a current to flow only from the ground terminal to the I/O terminal (implicit).
Regarding claim 11, Xu and Wang teach the I/O interface according to claim 10, wherein the first unilateral conductive element and the second unilateral conductive element each comprise a diode or a MOS transistor (implicit)(refer to Xu fig.1).
Regarding claim 14, Xu teaches an integrated circuit (refer to fig.1), comprising an input/output (I/O) interface (i.e. electrostatic protection circuit 100)(fig.1), comprising: an I/O terminal (i.e. IN)(fig.1); and a gate component (i.e. transistor MN3 and control module 14)(fig.1), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor MN3)(fig.1), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Xu does not teach an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Xu to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch.
Claim(s) 1-5, 7-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. Chinese Patent Document CN 103795026 B (hereinafter “Wang2”) and further in view of Wang.
Regarding claim 1, Wang2 teaches an input/output (I/O) interface (refer to fig.2), comprising: an I/O terminal (i.e. IN)(fig.2); and a gate component (i.e. transistor Mnt and inverters INV1 and INV2)(fig.2), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor Mnt)(fig.2), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Wang2 does not teach an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the input/output (I/O) interface of Wang2 to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch.
Regarding claim 2, Wang2 and Wang teach the I/O interface according to claim 1, wherein the input end of the first switch component is directly connected to the I/O terminal (implicit)(Refer to Wang2 fig.2).
Regarding clam 3, Wang2 and Wang teach the I/O interface according to claim 2, wherein the first switch component comprises a metal oxide semiconductor (MOS) transistor (i.e. Wang2 transistor Mnt)(fig.2)(i.e. Wang MOSFET 102)(fig.1), and the input end of the first switch component comprises a source electrode or a drain electrode of the MOS transistor (implicit)(refer to Wang2 transistor Mnt)(fig.1).
Regarding claim 4, Wang2 and Wang teach the I/O interface according to claim 1, wherein the anti-electrostatic discharge apparatus comprises a second switch component (i.e. Wang diode-connected MOSFET 110)(fig.1), and an output end of the second switch component is connected to a gate electrode of the first switch component (implicit)(refer to Wang fig.1).
Regarding claim 5, Wang2 and Wang teach the I/O interface according to claim 4, wherein the gate component further comprises a phase inverter (i.e. Wang inverters INV1 and INV2)(fig.2) connected to an input end of the second switch component (implicit)(refer to Wang gate)(fig.1).
Regarding claim 7, Wang2 and Wang teach the I/O interface according to claim 4, wherein the first switch component and the second switch component each comprise a metal oxide semiconductor field-efficient transistor (MOS FET) (refer to Wang diode-connected MOSFET 110 and MOSFET 102)(fig.1)(refer also to Wang2 transistor Mnt)(fig.1).
Regarding claim 8, Wang2 and Wang teach the I/O interface according to claim 4, wherein the second switch component comprises a MOS transistor (implicit)(refer to Wang diode-connected MOSFET 110)(fig.1), and the output end comprises a source electrode or a drain electrode of the MOS transistor (implicit)(refer to Wang fig.1).
Regarding claim 9, Wang2 and Wang teach the I/O interface according to claim 1, further comprising: a positive terminal (i.e. Wang2 VDD)(fig.2); a ground terminal (i.e. Wang2 VSS)(fig.2); and a discharge bridge (i.e. Wang2 diodes D1-D4)(fig.2) connected between the positive terminal and the ground terminal (implicit); however they do not teach the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the input/output (I/O) interface of Wang2 and Wang to include the discharge bridge comprising a current resistance smaller than a current resistance at the first switch component, to allow static electricity from the I/O terminal to be discharged through the discharge bridge to provide the advantage of ensuring proper operation of the circuit.
Regarding claim 10, Wang2 and Wang teach the I/O interface according to claim 9, wherein the discharge bridge comprises a first unilateral conductive element (i.e. Wang2 diodes D1 and D2)(fig.2) connected between the I/O terminal and the positive terminal (implicit) and a second unilateral conductive element (i.e. Wang2 diodes D3 and D4)(fig.2) connected between the I/O terminal and the ground terminal (implicit), wherein the first unilateral conductive element is configured to allow a current to flow only from the I/O terminal to the positive terminal (implicit), and the second unilateral conductive element is configured to allow a current to flow only from the ground terminal to the I/O terminal (implicit).
Regarding claim 11, Wang2 and Wang teach the I/O interface according to claim 10, wherein the first unilateral conductive element and the second unilateral conductive element each comprise a diode or a MOS transistor (implicit)(refer to Wang2 fig.2).
Regarding claim 12, Wang2 and Wang teach the I/O interface according to claim 9, further comprising a clamping circuit (i.e. Wang2 transistor Mbig)(fig.2) arranged between the positive terminal and the ground terminal (implicit).
Regarding claim 14, Wang2 teaches an integrated circuit (refer to fig.2), comprising an input/output (I/O) interface (refer to fig.2), comprising: an I/O terminal (i.e. IN)(fig.2); and a gate component (i.e. transistor Mnt and inverters INV1 and INV2)(fig.2), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor Mnt)(fig.2), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Wang2 does not teach an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Wang2 to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu and further in view of Wang and Dai et al. U.S. Patent Application 2017/0163032 (hereinafter “Dai”).
Regarding claim 13, Xu teaches a circuit (refer to fig.1), comprising an input/output (I/O) interface (i.e. electrostatic protection circuit 100)(fig.1), comprising: an I/O terminal (i.e. IN)(fig.1); and a gate component (i.e. transistor MN3 and control module 14)(fig.1), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor MN3)(fig.1), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Xu does not teach the circuit being a signal amplifier; and an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Xu to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch. However, Xu and Wang do not teach the circuit being a signal amplifier. However, Dai teaches the circuit being a signal amplifier (refer to [0016]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Wang2 and Wang to include the signal amplifier of Dai to provide the advantage of protecting a circuit that is susceptible to ESD, such as a signal amplifier, from damage due to ESD.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang2 and further in view of Wang and Dai.
Regarding claim 13, Wang2 teaches a circuit (refer to fig.2), comprising an input/output (I/O) interface (refer to fig.2), comprising: an I/O terminal (i.e. IN)(fig.2); and a gate component (i.e. transistor Mnt and inverters INV1 and INV2)(fig.2), configured to control reading of data from the I/O terminal (implicit), and comprising: a first switch component (i.e. transistor Mnt)(fig.2), wherein an input end of the first switch component is connected to the I/O terminal (implicit); however, Wang2 does not teach the circuit being a signal amplifier; and an anti-electrostatic discharge apparatus, configured to increase a breakdown voltage at the first switch component. However, Wang teaches an anti-electrostatic discharge apparatus (i.e. diode-connected MOSFET 110)(fig.1), configured to increase a breakdown voltage at the first switch component (implicit)(refer to MOSFET 102)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Wang2 to include the apparatus of Wang to provide the advantage of adjusting the triggering voltage of the first switch to allow for the use of a smaller switch. However, Wang2 and Wang do not teach the circuit being a signal amplifier. However, Dai teaches the circuit being a signal amplifier (refer to [0016]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Wang2 and Wang to include the signal amplifier of Dai to provide the advantage of protecting a circuit that is susceptible to ESD, such as a signal amplifier, from damage due to ESD.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 6 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 6, especially wherein a gate electrode of the second switch component and an input end of the phase inverter are synchronously controlled.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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