DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Claim Objections
Claims 1 and 12 objected to because of the following informalities: Claim 1 reads “perform the refresh operation responsive the first refresh signal” and “perform the refresh operation responsive a second refresh command”. The claim should read “perform the refresh operation responsive to the …”, in line with the previous claim limitations. Other claims contain similar informalities, such as dependent claim 12 which recites “… from the power down mode to the normal mode responsive the second power down signal”. The claim should be written as “responsive to the second power down signal”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (US Publication No. 2016/0267962 – “Saito”).
Regarding claim 1, Saito teaches An apparatus comprising: a plurality of external terminals including a plurality of command terminals; (Saito paragraph [0038], The semiconductor 10 according to various embodiments may include a so-called “per DRAM addressability function.” The per DRAM addressability function may be a function that inputs a selection signal to the data input-output terminal 21 in synchronization with the command signal CMD to make it possible to select whether or not to accept the command signal CMD. External command terminals can be used to receive commands) a memory cell array; (Saito paragraph [0023], The semiconductor device 10 may be DRAMs integrated in one semiconductor chip, and, as shown in FIG. 1, may include a memory cell array 11 divided into n+1 banks. The banks are units that can independently execute commands, and can basically perform nonexclusive operations) a refresh controller configured to control a refresh operation of the memory cell array; (Saito paragraph [0071], In some embodiments, a system includes a memory controller configured to issue a plurality of commands that includes a read command, a write command and a refresh command, the refresh command including first command information or second command information, and a plurality of memory devices configured to receive the commands in common from the memory controller. Commands including refresh commands can be sent from a memory controller (i.e., refresh controller)) a command decoder coupled to the plurality of command terminals and configured to: (Saito paragraph [0028], The address terminal 27 receives an address signal ADD. The supplied address signal ADD is supplied to a row control circuit 51, a column control circuit 52, a mode register 42, a command decoder 43, a multi-purpose register 53, and the like. A command decoder may be coupled to command terminals, also see Fig. 1; Ref #43 and #28 for external terminals) activate a first refresh signal responsive to a first refresh command supplied to the plurality of command terminals; and activate a first power down signal responsive to a power down entry command supplied to the plurality of command terminals; (Saito paragraph [0036], The command decoder 43 receives commands, in addition to the self-refresh entry commands SRE1 and SRE2, a refresh command REF, a self-refresh exit command SRX, a deep power down entry command DPD, and the like. A refresh signal can be performed responsive to a first refresh command, similar to the power down command responsive to a power down signal sent through the controller) and a power down controller configured to change an operation mode from a normal mode to a power down mode responsive to the first power down signal, (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The self-refresh exit command SRX is a command to return the semiconductor device 10 in the self-refresh mode to the normal mode. The deep power down entry command DPD is a command to enter the semiconductor device 10 into the deep power down mode. A power down mode can be entered in response to a power down command) wherein the refresh controller is configured to: perform the refresh operation responsive the first refresh signal in the normal mode; (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The refresh command can be executed in a normal operation mode) and perform the refresh operation responsive a second refresh command supplied to one of the plurality of external terminals in the power down mode (Saito Fig. 9; see t1-t3, also see Saito paragraph [0048], In some embodiments, as shown in FIG. 4, the DRAMs #0 to #3 may operate in the normal mode, and the DRAMs #4 to #7 may enter into the deep power down mode. In this case, the refresh command REF may be input or issued to the DRAMs #0 to #3 at time t1, and, at time t2 immediately after time t1, an exit command EXIT may be input or issued for returning the DRAMs #4 to #7 from the deep power down mode to the normal mode. In this case, because the DRAMs #0 to #3 operate in the normal mode, the data in the DRAMs #0 to #3 can be retained. Thus, the next refresh command REF may be issued at time t3 at which tREFI×9 time passes. A second refresh command can be issued when in the power down mode).
Regarding claim 2, Saito teaches The apparatus of claim 1, wherein the plurality of external terminals include a clock terminal supplied with an external clock signal, wherein the apparatus further comprises a clock input circuit coupled to the clock terminal and configured to generate an internal clock signal based on the external clock signal, (See Saito Fig. 1; Ref #24 & #40 for external clock signal, also see Saito paragraph [0025], The semiconductor device 10 has, in addition to the data input-output terminal 21, as external terminals, strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminals 30, 31 and 34, a data mask terminal 32, and an ODT terminal 33) and wherein the clock input circuit is activated in the normal mode and deactivated in the power down mode (Saito paragraph [0052], As shown in FIG. 10, each of the first input pattern (A) and the second input pattern (B) has a waveform in which the clock enable signal CKE transitions from an active level to an inactive level and, thereafter, the chip select signal /CS transitions from an inactive level to an active level. A difference between the waveforms is a time span from a time when the clock enable signal CKE changes to another time when the chip select signal /CS changes. The clock can be in an active or inactive level, corresponding to a normal and power down operation mode, such as described in Saito paragraph [0054], Since the semiconductor device 10 that enters into the deep power down mode does not receive the clock signals CK and /CK, the semiconductor device 10 is not in synchronization with the clock signals).
Regarding claim 3, Saito teaches The apparatus of claim 1, wherein one of the plurality of command terminals is supplied with a power down exit command, (Saito paragraph [0049], However, in this case, since the exit command EXIT is issued at time t2, returning operations from the deep power down mode are started with respect to the DRAMs #4 to #7. When a long time (for example, about several hundred μs), longer in time than tREFI×9 (the maximum issue cycle time), is experienced, until the DRAMs return from the deep power down mode into the normal mode, in the middle of the returning operations from the deep power down mode. The power down mode can be executed to resume normal operation) wherein the apparatus further comprises a first detector coupled to the one of the plurality of command terminals and configured to activate a second power down signal based on the power down exit command, and wherein the power down controller is configured to change an operation mode from the power down mode to the normal mode responsive to the second power down signal (Saito paragraph [0069], As described above, according to some embodiments, the command signal CMD having the first input pattern (A) is input to cause the DRAMs #0 to #3 operated in the normal mode to enter into the self-refresh mode, and to cause the DRAMs #4 to #7 enter into the deep power down mode to return from the deep power down mode and, thereafter, to automatically enter into the self-refresh mode. In this manner, even though a long time may be taken to return from the deep power down mode, data in the DRAMs #0 to #3 operated in the normal mode may not be lost. To exit the power down mode an operation exit signal may be received to return to normal operation mode, for additional details regarding exiting a power down mode, see Saito paragraph [0021], However, when only some DRAMs configured in the same rank are entered into a predetermined operation mode, access to other DRAMs may not be executed for a period required for a return from the predetermined operation mode to the normal mode. For example, when only some DRAMs configured in the same rank enter into the deep power down mode, for the period required for a return from the deep power down mode to the normal mode, a refresh command might not be input to other DRAMs. Since a relatively long time is required to return from the deep power down mode, there might be a risk that a refresh command cannot be issued for other DRAMs within a maximum issue cycle of a refresh command regulated by the specifications. For a detector component, see Saito paragraph [0037] which discloses a circuit performing a detection for a refresh command).
Regarding claim 4, Saito teaches The apparatus of claim 3, wherein the first detector is activated in the power down mode and deactivated in the normal mode (Saito paragraph [0069], As described above, according to some embodiments, the command signal CMD having the first input pattern (A) is input to cause the DRAMs #0 to #3 operated in the normal mode to enter into the self-refresh mode, and to cause the DRAMs #4 to #7 enter into the deep power down mode to return from the deep power down mode and, thereafter, to automatically enter into the self-refresh mode. In this manner, even though a long time may be taken to return from the deep power down mode, data in the DRAMs #0 to #3 operated in the normal mode may not be lost. To exit the power down mode an operation exit signal may be received to return to normal operation mode, for additional details regarding exiting a power down mode).
Regarding claim 5, Saito teaches The apparatus of claim 1, further comprising a second detector coupled to the one of the plurality of external terminals and configured to activate a second refresh signal based on the second refresh command, wherein the refresh controller is configured to perform the refresh operation responsive the second refresh signal, (Saito paragraph [0028], The address terminal 27 receives an address signal ADD. The supplied address signal ADD is supplied to a row control circuit 51, a column control circuit 52, a mode register 42, a command decoder 43, a multi-purpose register 53, and the like. The row control circuit 51 is a circuit block including an address buffer, a refresh counter, and the like, and controls the row decoder 12 on the basis of a row address. The command terminals may receive multiple refresh commands and include a refresh counter, which can be performed repeatedly, such as described in Saito paragraph [0030], The command decoder 43 includes a judgment circuit 43a. The judgment circuit 43a, as shown in FIG. 2, receives the clock enable signal CKE and the chip select signal /CS to determine an entry to a self-refresh mode. The self-refresh mode is a type of standby mode, and is an operation mode that automatically executes a refresh operation on the memory cell array 11 under the control of the row control circuit 51) and wherein the second detector is activated in the power down mode and deactivated in the normal mode (Saito paragraph [0069], As described above, according to some embodiments, the command signal CMD having the first input pattern (A) is input to cause the DRAMs #0 to #3 operated in the normal mode to enter into the self-refresh mode, and to cause the DRAMs #4 to #7 enter into the deep power down mode to return from the deep power down mode and, thereafter, to automatically enter into the self-refresh mode. In this manner, even though a long time may be taken to return from the deep power down mode, data in the DRAMs #0 to #3 operated in the normal mode may not be lost. To exit the power down mode an operation exit signal may be received to return to normal operation mode, for additional details regarding exiting a power down mode).
Regarding claim 6, Saito teaches The apparatus of claim 5, wherein the one of the plurality of external terminals is included in the plurality of command terminals (Saito paragraphs [0029-0030], The semiconductor device 10 has, in addition to the data input-output terminal 21, as external terminals, strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminals 30, 31 and 34, a data mask terminal 32, and an ODT terminal 33. The strobe terminals 22 and 23 are terminals to input/output external strobe signals DQST and DQSB. The external strobe signals DQST and DQSB are complementary signals that regulate input/output timing of data input/output through the data input-output terminal 21. In some embodiments, when data is input, for example in a write operation, the external strobe signals DQST and DQSB are supplied to a strobe circuit 18, and the strobe circuit 18 controls an operation timing of the data input-output circuit 17 on the basis of the external strobe signals DQST and DQSB. In this manner, the write data input through the data input-output terminal 21 is taken into the data input-output circuit 17 in synchronization with the external strobe signals DQST and DQSB. The command terminals may include a plurality of terminals including external signal terminals).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-10 and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (US Publication No. 2016/0267962 – “Saito”) in view of Nishijima (US Publication No. 2012/0294096 – “Nishijima”).
Regarding claim 7, Saito teaches An apparatus comprising: a memory cell array; a plurality of command terminals supplied with an external command; (Saito paragraph [0038], The semiconductor 10 according to various embodiments may include a so-called “per DRAM addressability function.” The per DRAM addressability function may be a function that inputs a selection signal to the data input-output terminal 21 in synchronization with the command signal CMD to make it possible to select whether or not to accept the command signal CMD. External command terminals can be used to receive commands) a command decoder coupled to the plurality of command terminals and configured to (Saito paragraph [0028], The address terminal 27 receives an address signal ADD. The supplied address signal ADD is supplied to a row control circuit 51, a column control circuit 52, a mode register 42, a command decoder 43, a multi-purpose register 53, and the like. A command decoder may be coupled to command terminals, also see Fig. 1; Ref #43 and #28 for external terminals) activate a first power down signal when the external command indicates a power down entry command; (Saito paragraph [0036], The command decoder 43 receives commands, in addition to the self-refresh entry commands SRE1 and SRE2, a refresh command REF, a self-refresh exit command SRX, a deep power down entry command DPD, and the like. A refresh signal can be performed responsive to a first refresh command, similar to the power down command responsive to a power down signal sent through the controller) a power down controller configured to change an operation mode from a normal mode to a power down mode responsive to the first power down signal; (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The self-refresh exit command SRX is a command to return the semiconductor device 10 in the self-refresh mode to the normal mode. The deep power down entry command DPD is a command to enter the semiconductor device 10 into the deep power down mode. A power down mode can be entered in response to a power down command) a refresh controller configured to perform a refresh operation … (Saito paragraph [0071], In some embodiments, a system includes a memory controller configured to issue a plurality of commands that includes a read command, a write command and a refresh command, the refresh command including first command information or second command information, and a plurality of memory devices configured to receive the commands in common from the memory controller. Commands including refresh commands can be sent from a memory controller (i.e., refresh controller))
Saito does not teach perform a refresh operation of the memory cell array when a potential of a first one of the plurality of command terminals exceeds a first predetermined level in the power down mode.
However, Nishijima teaches perform a refresh operation of the memory cell array when a potential of a first one of the plurality of command terminals exceeds a first predetermined level in the power down mode (Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito with those of Nishijima. Nishijima teaches using a threshold potential voltage value based on a command terminal comparison to determine whether to perform a refresh command, which may reduce power consumption in the memory device (Nishijima paragraph [0101], Further, in the level shifter 129 of the memory element 110 shown in FIG. 3, the inverter is provided between the wiring for supplying a high power supply potential V.sub.dd and the wiring for supplying a low power supply potential V.sub.ss; the through current from the wiring for supplying a high power supply potential V.sub.dd to the wiring for supplying a low power supply potential V.sub.ss can be reduced, and thus power consumption can be further reduced as compared with the case of the memory element in FIG. 2).
Regarding claim 8, Saito in view of Nishijima teaches The apparatus of claim 7, wherein the command decoder is configured to activate a first refresh signal when the external command indicates a refresh command, (Saito paragraph [0036], The command decoder 43 receives commands, in addition to the self-refresh entry commands SRE1 and SRE2, a refresh command REF, a self-refresh exit command SRX, a deep power down entry command DPD, and the like. A refresh signal can be performed responsive to a first refresh command, similar to the power down command responsive to a power down signal sent through the controller) and wherein the refresh controller is configured to perform the refresh operation responsive to the first refresh signal in the normal mode (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The refresh command can be executed in a normal operation mode).
Regarding claim 9, Saito in view of Nishijima teaches The apparatus of claim 8, further comprising a first detector coupled to the first one of the plurality of command terminals and configured to activate a second refresh signal when the potential of the first one of the plurality of command terminals exceeds the first predetermined level in the power down mode, (Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed) wherein the refresh controller is configured to perform the refresh operation responsive to the second refresh signal in the power down mode (Saito Fig. 9; see t1-t3, also see Saito paragraph [0048], In some embodiments, as shown in FIG. 4, the DRAMs #0 to #3 may operate in the normal mode, and the DRAMs #4 to #7 may enter into the deep power down mode. In this case, the refresh command REF may be input or issued to the DRAMs #0 to #3 at time t1, and, at time t2 immediately after time t1, an exit command EXIT may be input or issued for returning the DRAMs #4 to #7 from the deep power down mode to the normal mode. In this case, because the DRAMs #0 to #3 operate in the normal mode, the data in the DRAMs #0 to #3 can be retained. Thus, the next refresh command REF may be issued at time t3 at which tREFI×9 time passes. A second refresh command can be issued when in the power down mode).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito with those of Nishijima. Nishijima teaches using a threshold potential voltage value based on a command terminal comparison to determine whether to perform a refresh command, which may reduce power consumption in the memory device (Nishijima paragraph [0101], Further, in the level shifter 129 of the memory element 110 shown in FIG. 3, the inverter is provided between the wiring for supplying a high power supply potential V.sub.dd and the wiring for supplying a low power supply potential V.sub.ss; the through current from the wiring for supplying a high power supply potential V.sub.dd to the wiring for supplying a low power supply potential V.sub.ss can be reduced, and thus power consumption can be further reduced as compared with the case of the memory element in FIG. 2).
Regarding claim 10, Saito in view of Nishijima teaches The apparatus of claim 9, wherein the first detector is activated in the power down mode and deactivated in the normal mode (Saito paragraph [0037], A circuit for returning the semiconductor device 10 from the deep power down mode to the normal mode is still activated in the deep power down mode, such that the returning circuit can detect a deep power down mode exit command input from the outside. For this reason, the data in the memory cell array 11 is reduced or even eliminated, and a current consumption is further reduced in comparison with the self-refresh mode. Since the mode can easily be set by storing the value into the mode register 42 and the like, returning the semiconductor device 10 from the deep power down mode may be performed at a speed higher than that of an initializing operation performed when the reset signal RST is input. A circuit may have a value initiated indicating an active and inactive state based on a power down mode and a normal mode).
Regarding claim 14, Saito in view of Nishijima teaches The apparatus of claim 7, further comprising: a clock terminal supplied with an external clock signal; and a clock input circuit coupled to the clock terminal and configured to generate an internal clock signal based on the external clock signal, (See Saito Fig. 1; Ref #24 & #40 for external clock signal, also see Saito paragraph [0025], The semiconductor device 10 has, in addition to the data input-output terminal 21, as external terminals, strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminals 30, 31 and 34, a data mask terminal 32, and an ODT terminal 33) wherein the clock input circuit is activated in the normal mode and deactivated in the power down mode (Saito paragraph [0052], As shown in FIG. 10, each of the first input pattern (A) and the second input pattern (B) has a waveform in which the clock enable signal CKE transitions from an active level to an inactive level and, thereafter, the chip select signal /CS transitions from an inactive level to an active level. A difference between the waveforms is a time span from a time when the clock enable signal CKE changes to another time when the chip select signal /CS changes. The clock can be in an active or inactive level, corresponding to a normal and power down operation mode, such as described in Saito paragraph [0054], Since the semiconductor device 10 that enters into the deep power down mode does not receive the clock signals CK and /CK, the semiconductor device 10 is not in synchronization with the clock signals).
Regarding claim 15, Saito in view of Nishijima teaches The apparatus of claim 14, wherein the internal clock signal is supplied to the command decoder (Saito paragraph [0027], The clock generator 40 is activated on the basis of a clock enable signal CKE input through the clock enable terminal 26 to generate an internal clock signal ICLK. The external clock signals CK and /CK supplied through the clock terminals 24 and 25 are also supplied to a DLL circuit 41. The DLL circuit 41 generates an output clock signal LCLK controlled in phase on the basis of the external clock signals CK and /CK. The output clock signal LCLK is used as a timing signal that regulates an output timing of read data output by the data input-output circuit 17. An internal clock signal may be generated for command operation (i.e., transmitted to the command operation signal).
Regarding claim 16, Saito teaches A system comprising: a memory chip having a plurality of external terminals; (Saito paragraph [0038], The semiconductor 10 according to various embodiments may include a so-called “per DRAM addressability function.” The per DRAM addressability function may be a function that inputs a selection signal to the data input-output terminal 21 in synchronization with the command signal CMD to make it possible to select whether or not to accept the command signal CMD. External command terminals can be used to receive commands) and a controller chip coupled to the plurality of external terminals of the memory chip and configured to issue, via some of the plurality of external terminals, a plurality of commands including a power down entry command and a refresh command, (Saito paragraph [0028], The address terminal 27 receives an address signal ADD. The supplied address signal ADD is supplied to a row control circuit 51, a column control circuit 52, a mode register 42, a command decoder 43, a multi-purpose register 53, and the like. A command decoder may be coupled to command terminals, also see Fig. 1; Ref #43 and #28 for external terminals. For a memory chip issuing a plurality of commands through terminals, also see Saito paragraph [0030], The command decoder 43 includes a judgment circuit 43a. The judgment circuit 43a, as shown in FIG. 2, receives the clock enable signal CKE and the chip select signal /CS to determine an entry to a self-refresh mode. The self-refresh mode is a type of standby mode, and is an operation mode that automatically executes a refresh operation on the memory cell array 11 under the control of the row control circuit 51. When the semiconductor device enters into the self-refresh mode, although the data in the memory cell array 11 is held, the semiconductor device will not accept an external access. Since most of the circuit blocks are inactivated, current consumption may become very low. Readers that desire to learn more about the self-refresh mode or command may refer to U.S. Pat. No. 7,742,356 (which is a counterpart application of JP2008-146687). The disclosure of U.S. Pat. No. 7,742,356 is incorporated herein by reference thereto in its entirety. The circuits, such as the command decoder 43, the control logic circuit 44, the row control circuit 51, the column control circuit 52, the data input-output circuit 17, the FIFO circuit 16, the data controller 15, or the row and column decoders 12 and 13, can be referred to as access circuits) wherein the memory chip is configured to: change an operation mode from a normal mode to a power down mode when the power down entry command is issued from the controller chip; (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The self-refresh exit command SRX is a command to return the semiconductor device 10 in the self-refresh mode to the normal mode. The deep power down entry command DPD is a command to enter the semiconductor device 10 into the deep power down mode. A power down mode can be entered in response to a power down command) perform a refresh operation when the refresh command is issued from the controller chip in the normal mode; (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The refresh command can be executed in a normal operation mode).
Saito does not teach perform the refresh operation when the controller chip brings one of the plurality of external terminals into a first predetermined level in the power down mode.
However, Nishijima teaches perform the refresh operation when the controller chip brings one of the plurality of external terminals into a first predetermined level in the power down mode (Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito with those of Nishijima. Nishijima teaches using a threshold potential voltage value based on a command terminal comparison to determine whether to perform a refresh command, which may reduce power consumption in the memory device (Nishijima paragraph [0101], Further, in the level shifter 129 of the memory element 110 shown in FIG. 3, the inverter is provided between the wiring for supplying a high power supply potential V.sub.dd and the wiring for supplying a low power supply potential V.sub.ss; the through current from the wiring for supplying a high power supply potential V.sub.dd to the wiring for supplying a low power supply potential V.sub.ss can be reduced, and thus power consumption can be further reduced as compared with the case of the memory element in FIG. 2).
Regarding claim 17, Saito in view of Nishijima teaches The system of Claim 16, wherein the memory chip includes a first detector coupled to the one of the plurality of external terminals, and wherein the first detector is activated in the power down mode and configured to detect that a potential of the one of the plurality of external terminals reaches the first predetermined level (Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito with those of Nishijima. Nishijima teaches using a threshold potential voltage value based on a command terminal comparison to determine whether to perform a refresh command, which may reduce power consumption in the memory device (Nishijima paragraph [0101], Further, in the level shifter 129 of the memory element 110 shown in FIG. 3, the inverter is provided between the wiring for supplying a high power supply potential V.sub.dd and the wiring for supplying a low power supply potential V.sub.ss; the through current from the wiring for supplying a high power supply potential V.sub.dd to the wiring for supplying a low power supply potential V.sub.ss can be reduced, and thus power consumption can be further reduced as compared with the case of the memory element in FIG. 2).
Regarding claim 18, Saito in view of Nishijima teaches The system of claim 17, wherein the plurality of external terminals include a plurality of command terminals supplied with the plurality of commands, and wherein the one of the plurality of external terminals is included in the plurality of command terminals (Saito paragraphs [0029-0030], The semiconductor device 10 has, in addition to the data input-output terminal 21, as external terminals, strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminals 30, 31 and 34, a data mask terminal 32, and an ODT terminal 33. The strobe terminals 22 and 23 are terminals to input/output external strobe signals DQST and DQSB. The external strobe signals DQST and DQSB are complementary signals that regulate input/output timing of data input/output through the data input-output terminal 21. In some embodiments, when data is input, for example in a write operation, the external strobe signals DQST and DQSB are supplied to a strobe circuit 18, and the strobe circuit 18 controls an operation timing of the data input-output circuit 17 on the basis of the external strobe signals DQST and DQSB. In this manner, the write data input through the data input-output terminal 21 is taken into the data input-output circuit 17 in synchronization with the external strobe signals DQST and DQSB. The command terminals may include a plurality of terminals including external signal terminals).
Claim(s) 11 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Nishijima as applied to claims 7 and 18 above, and further in view of Hoshino et al. (US Publication No. 2023/0291018 – “Hoshino”).
Regarding claim 11, Saito in view of Nishijima in further view of Hoshino teaches The apparatus of claim 7, wherein the power down controller is configured to change an operation mode from the power down mode to the normal mode when a potential of a second one of the plurality of command terminals (Hoshino paragraphs [0030-0031], Next, upon connection of a charger to the external terminal, the voltage of the external terminal voltage input port VM is lower than the ground terminal voltage VSS. The detector 113 detects that an L-level power-down control signal is received at the input port, and outputs an H-level power-down release signal PD_R from the output port of the inverter B. Upon receiving the H-level power-down release signal PD_R, the control circuit 112 releases the power-down state. That is, the control circuit 112 turns on the discharge control FET 12 via the discharge control terminal DO to turn on the switches 114 and 115. As described above, in the battery device 10, the power-down detection signal PD_D and the power-down release signal PD_R are outputted by the detector 113, which detects the voltage of the external terminal voltage input port VM, to transition to and release the power down state. An operation mode/state can be changed based on a detected potential of an external terminal) exceeds a second predetermined level in the power down mode (See Nishijima for reference to detecting a voltage compared to a predetermined level, as described above in Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito and Nishijima with those of Hoshino. Hoshino teaches transitioning between operation modes/states based on a detected voltage level of external terminals, which can minimize the amount of power-down detection circuits required reducing the cost of chips and packages (i.e., see Hoshino paragraph [0032], As described above, the charge and discharge control circuit of the present embodiment is configured to input the power-down control signal according to the H-level signal of the FET controlled by the controller, so it becomes possible to use the external terminal voltage input port VM also as a control signal input port. Also, the detection circuit is composed of a Schmitt trigger circuit, so it has noise immunity and can output a power-down detection signal and a power-down release signal without requiring an additional circuit. Thus, in the charge and discharge control circuit of the present embodiment, the number of pins can be reduced without increasing the number of circuits, which makes it possible to reduce the cost of chips and packages).
Regarding claim 19, Saito in view of Nishijima in further view of Hoshino teaches The system of claim 18, wherein the memory chip is configured to change an operation mode from the power down mode to the normal mode when the controller chip brings another of the plurality of external terminals (Hoshino paragraphs [0030-0031], Next, upon connection of a charger to the external terminal, the voltage of the external terminal voltage input port VM is lower than the ground terminal voltage VSS. The detector 113 detects that an L-level power-down control signal is received at the input port, and outputs an H-level power-down release signal PD_R from the output port of the inverter B. Upon receiving the H-level power-down release signal PD_R, the control circuit 112 releases the power-down state. That is, the control circuit 112 turns on the discharge control FET 12 via the discharge control terminal DO to turn on the switches 114 and 115. As described above, in the battery device 10, the power-down detection signal PD_D and the power-down release signal PD_R are outputted by the detector 113, which detects the voltage of the external terminal voltage input port VM, to transition to and release the power down state. An operation mode/state can be changed based on a detected potential of an external terminal) into a second predetermined level in the power down mode (See Nishijima for reference to detecting a voltage compared to a predetermined level, as described above in Nishijima paragraph [0103], FIG. 4 is a timing chart in which solid lines indicate the high power supply potential V.sub.dd and the potentials of the first terminal D, the second terminal DB, the node N1, and the node N2 in the refresh operation performed after supplying power is stopped in the state where the potential Low (0 V) is applied to the node N1 and the potential V.sub.hold is applied to the node N2. FIG. 5 to FIG. 10 are circuit diagrams of the memory element in periods t1 to t6. In FIG. 5 to FIG. 10, cross marks are put on the transistors in an off state. Note that the potential V.sub.hold refers to a voltage that is lower than the high power supply potential V.sub.dd (High) by the threshold voltage of an n-channel transistor (V.sub.th.sub.--n), which satisfies the relation, Low<V.sub.th.sub.--n<V.sub.hold<High. A potential voltage comparison may be performed in a power down mode (i.e., low power state) to determine whether or not a refresh operation is performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito and Nishijima with those of Hoshino. Hoshino teaches transitioning between operation modes/states based on a detected voltage level of external terminals, which can minimize the amount of power-down detection circuits required reducing the cost of chips and packages (i.e., see Hoshino paragraph [0032], As described above, the charge and discharge control circuit of the present embodiment is configured to input the power-down control signal according to the H-level signal of the FET controlled by the controller, so it becomes possible to use the external terminal voltage input port VM also as a control signal input port. Also, the detection circuit is composed of a Schmitt trigger circuit, so it has noise immunity and can output a power-down detection signal and a power-down release signal without requiring an additional circuit. Thus, in the charge and discharge control circuit of the present embodiment, the number of pins can be reduced without increasing the number of circuits, which makes it possible to reduce the cost of chips and packages).
Regarding claim 20, Saito in view of Nishijima in further view of Hoshino teaches The system of claim 19, wherein the memory chip includes a second detector coupled to the another of the plurality of external terminals, (Saito paragraph [0037], The refresh command REF will be input when a refresh operation is executed, and will be periodically input in a normal mode. The self-refresh exit command SRX is a command to return the semiconductor device 10 in the self-refresh mode to the normal mode. The deep power down entry command DPD is a command to enter the semiconductor device 10 into the deep power down mode. The deep power down mode is a kind of standby mode that may inactivate most of the circuit blocks including the power supply circuit 46 configuring the semiconductor device 10, and the self-refresh operation is also not executed. A circuit for returning the semiconductor device 10 from the deep power down mode to the normal mode is still activated in the deep power down mode, such that the returning circuit can detect a deep power down mode exit command input from the outside. An external connection/terminal may be coupled to a circuit performing refresh operation detection) and wherein the second detector is activated in the power down mode and configured to detect that a potential of the another of the plurality of external terminals reaches the second predetermined level (Nishijima paragraph [0069], Further, the signals output from the level shifter L are input to the level shifter L via the buffer B1 and the buffer B2; the output data of the level shifter L is fed back accordingly. In other words, the memory element M functions as a nonvolatile latch. Even if the potentials held at the node N1 and the node N2 fluctuate due to the long stop of supplying power, the potentials of the node N1 and the node N2 can be refreshed when power is supplied, and thus change in data of the memory element can be reduced. A different node/terminal may have a second predetermined value for potential to change an operation mode).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Saito with those of Nishijima. Nishijima teaches using a threshold potential voltage value based on a command terminal comparison to determine whether to perform a refresh command, which may reduce power consumption in the memory device (Nishijima paragraph [0101], Further, in the level shifter 129 of the memory element 110 shown in FIG. 3, the inverter is provided between the wiring for supplying a high power supply potential V.sub.dd and the wiring for supplying a low power supply potential V.sub.ss; the through current from the wiring for supplying a high power supply potential V.sub.dd to the wiring for supplying a low power supply potential V.sub.ss can be reduced, and thus power consumption can be further reduced as compared with the case of the memory element in FIG. 2).
Allowable Subject Matter
Claims 12-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 12 is indicated as objected to for containing allowable subject matter but being dependent upon a rejected claim. Dependent claim 12 depends upon dependent claim 11, and further recites details regarding the changing of operation mode of a power down controller based on a potential of a plurality of commands terminals exceeding a second predetermine level while operating in the power down mode. Claim 12 further recites activating a second power down signal when the potential of the second one of the plurality of command terminals exceeds the second predetermined level in the power down mode, wherein the power down controller is configured to change an operation mode from the power down mode to the normal mode responsive to the second power down signal. The specific details regarding the management of the power down controller changing operation mode based on the detected potential of the plurality of external command terminals compared to a second distinct predetermined level while in a particular operating mode is not taught in the technological field and is objected to. Dependent claim 13 depends upon dependent claim 12 and is similarly objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamakoshi (US Publication No. 2018/0090501) teaches a power detection circuit which can detect a voltage value at external terminals, and determine whether the voltage is less than a predetermined judgement voltage, which can allow for a power-off state to occur (i.e., see Yamakoshi paragraph [0042], The power-off detection circuit VDET monitors the power supply voltage VDD at the external terminal PNv1 and detects the power cutoff. Although not restricted in particular, the power-off detection circuit VDET is comprised of a comparator, and asserts a power-off detection signal POFF when the state where the voltage value at the external terminal PNv1 is less than a predetermined judgment voltage has continued for a predetermined period of time. The write voltage generating circuit VPPG is a step-up circuit and steps up the power supply voltage VDD to generate a write voltage VPP higher than the power supply voltage VDD).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached Monday - Friday 8 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571)-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
