DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment to claim 10 submitted on July 8, 2026, appears to overcome the Objection to the Claims. Therefore, the Objection to the Claims is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN-113687771-A), hereafter referred to as Lin’771 in view of Sehgal et al. (US 2023/0236742), hereafter referred to as Sehgal’742.
Referring to independent claim 1, Lin’771 teaches a memory sub-system, comprising: a host interface operable on a connection from the host interface to a host system outside of the memory sub-system (transmission interface circuit 118, see figure 1 and paragraph 54, line 3); random access memory cells (random memory access 116, see figure 1 and paragraph 54, line 2) configured to provide a memory space accessible to the host system (random access memory 116 may be used to provide an internal storage space (e.g., temporarily stored information), see figure 1 and paragraph 54, lines 4-5); and non-volatile memory cells (nonvolatile memory 120, see figure 1 and paragraph 54, lines 6-7) configured to provide a storage space accessible to the host system (memory controller 110 can use a response universal flash memory storage protocol information unit to the host device 50, see figure 1 and paragraph 58, lines 22-24).
Lin’771 does not appear to explicitly teach the memory space accessible to the host system over the connection via a memory access protocol and the storage space accessible to the host system over the connection via a storage access protocol.
However, Sehgal’742 teaches the memory space accessible to the host system over the connection via a memory access protocol (when the device controller 203 receives a conventional CXL.io packet, the embedded data will be sent directly to the CXL DRAM device 225, see figure 4B and paragraph 40, lines 8-11) and the storage space accessible to the host system over the connection via a storage access protocol (processing an NVMe memory command via a CXL.io protocol, paragraph 25, lines 1-2).
Lin’771 and Sehgal’742 are analogous because they are both drawn to the same inventive field of memory access.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771 and Sehgal’742 before them, to modify the memory sub-system of Lin’771 to include the access of memory and storage space over a connection by incorporating memory and storage connected remotely, and using NVMe, DMA, and CXL.io protocols.
The motivation for doing so would have been cost reductions in terms of using a single, common controller for both dynamic memory storage and non-volatile memory storage (paragraph 5, lines 7-9).
Therefore, it would have been obvious to combine Lin’771 and Sehgal’742 to bring about the invention as claimed.
Note that claim 18 contains the corresponding limitations of claim 1 as shown above; therefore, it is rejected using the same reasoning accordingly.
As to claim 2, Lin’771 anticipates the memory sub-system of claim 1, further comprising: a controller (memory controller 110, see figure 1 and paragraph 54, line 1) configured to execute a storage access request (host device 50 may be used to indicate at least one packet (e.g., read request) of the read request, see figure 1 and paragraph 60, lines 1-3), received from the host system over the connection according to the storage access protocol (universal flash memory storage protocol information unit of the device information field (Device Information field), paragraph 58, lines 24-25), to read data into the memory space from a logical block address in the storage space (memory controller 110 may load the area logic to the entity address mapping table from the non-volatile memory 120 to the random access memory 116 from the non-volatile memory 120, see figure 1 and paragraph 58, lines 12-14); wherein the data is read into the memory space at a plurality of memory addresses identified via the storage access request (random access memory 116 may be used to provide an internal storage space (e.g., temporarily stored information), see figure 1 and paragraph 54, lines 4-5); and the memory access protocol is usable by the host system to selectively access any of the plurality of memory addresses (host device 50 may send a plurality of host commands and a plurality of corresponding logic addresses to the memory controller 110, see figure 1 and paragraph 55, lines 1-2).
As to claim 3, Lin’771 anticipates the memory sub-system of claim 2, wherein the memory access protocol is usable by the host system to selectively write data (host device 50 sends at least one packet indicating at least one requirement, the memory controller 110 judges whether there is write requirement in at least one requirement, see figure 9, step S24 and paragraph 109, lines 2-4) to any of the plurality of memory addresses (when there is write requirement in at least one requirement, the memory controller 110 may be used to perform data writing on non-volatile memory 120, see figure 9, step S24 and paragraph 109, lines 3-5).
As to claim 4, Lin’771 anticipates the memory sub-system of claim 3, wherein the controller is further configured to execute a further storage access request, received according to the storage access protocol (host device 50 sends the at least one packet indicating the at least one requirement, see figure 9, step S14 and paragraph 102, lines 1-2), to write data available in the memory space at the plurality of memory addresses to the logical block address in the storage space (unit size may represent a predetermined unit size corresponding to a single logical address (e.g., a single logical block address), paragraph 102, lines 2-5).
Note that claim 19 contains the corresponding limitations of claim 4 as shown above; therefore, it is rejected using the same reasoning accordingly.
As to claim 5, Lin’771 teaches the memory sub-system of claim 4, wherein the random access memory cells are dynamic random access memory (DRAM) (DRAM, paragraph 53, lines 4-5) or static random access memory (SRAM) (SRAM, paragraph 53, line 5); the non-volatile memory cells are NAND or NOR flash memory (NAND flash memory, paragraph 57, lines 12-13); and the memory access protocol is in accordance with a standard for compute express link (CXL) or a standard for peripheral component interconnect express (PCIe, paragraph 54, line 13).
Lin’771 does not appear to explicitly teach wherein the storage access protocol is in accordance with a standard for non-volatile memory express (NVMe).
However, Sehgal’742 teaches wherein the storage access protocol is in accordance with a standard for non-volatile memory express (NVMe) (use of the NVMe protocol over the CXL.io protocol, paragraph 54, lines 4-5).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771 and Sehgal’742 before them, to modify the system of Lin’771 to include an NVMe-compliant storage access protocol by implementing the NVMe protocol over a CXL.io protocol.
The motivation for doing so would have been that the NVMe protocol is a commonly known protocol in the art of storage media, and that it would not have involved undue experimentation, nor would it have produced undesirable results.
Therefore, it would have been obvious to combine Lin’771 and Sehgal’742 to bring about the invention as claimed.
Referring to claim 9, Lin’771 teaches a method comprising: receiving, in a host interface of a memory sub-system over a connection between the host interface and a host system, a storage access request to access a logical block address in a storage space of the memory sub-system (memory controller 110 may load the area logic to the entity address mapping table from the non-volatile memory 120 to the random access memory 116 from the non-volatile memory 120, see figure 1 and paragraph 58, lines 12-14); and executing, by the memory sub-system, the storage access request (host device 50 may be used to indicate at least one packet (e.g., read request) of the read request, see figure 1 and paragraph 60, lines 1-3); receiving, in the host interface of the memory sub-system over the connection between the host interface and the host system, a memory access request (packet contains at least one initial logic address of the read request, paragraph 7, lines 10-13); and responding, by the memory sub-system, to the memory access request (memory controller 110 can use a response universal flash memory storage protocol information unit to the host device 50, see figure 1 and paragraph 58, lines 22-24).
Lin’771 does not appear to explicitly teach providing, by the memory sub-system, a completion record for the storage access request in accordance with a storage access protocol, the memory access request to access a memory address in a memory space of the memory sub-system, and the responding in accordance with a memory access protocol.
However, Sehgal’742 teaches providing, by the memory sub-system, a completion record for the storage access request in accordance with a storage access protocol (CQ 420 is a circular buffer used to post statuses for completed memory commands, see figure 4A and paragraph 30, lines 1-2), the memory access request to access a memory address in a memory space of the memory sub-system (the embedded data will be sent directly to the CXL DRAM device 225, see figure 4B and paragraph 40, lines 8-11); and the responding in accordance with a memory access protocol (when the device controller 203 receives a conventional CXL.io packet, the embedded data will be sent directly to the CXL DRAM device 225, see figure 4B and paragraph 40, lines 8-11).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771 and Sehgal’742 before them, to modify the method of Lin’771 to include the access of memory and storage space over a connection by incorporating memory and storage connected remotely, and using NVMe, DMA, and CXL.io protocols, and to include the completion record by having RAID mapping table entries replicated to a backup mapping table upon completion.
The motivation for doing so would have been cost reductions in terms of using a single, common controller for both dynamic memory storage and non-volatile memory storage (paragraph 5, lines 7-9).
Therefore, it would have been obvious to combine Lin’771 and Sehgal’742 to bring about the invention as claimed.
Claim(s) 7-8, 10-11, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin’771 and Sehgal’742 as applied to claim 3 above, and further in view of Hahn et al. (US 2023/0418518), hereafter referred to as Hahn’518.
As to claim 7, Lin’771 and Sehgal’742 do not appear to explicitly teach the memory sub-system of claim 3, wherein the controller is further configured to execute a further storage access request, received according to the storage access protocol, to read data into a memory device configured outside of the memory sub-system from the logical block address in the storage space.
However, Hahn’518 teaches the memory sub-system of claim 3, wherein the controller is further configured to execute a further storage access request, received according to the storage access protocol (other distributed operations may use space in remotely addressable memory 306 as requested by the master storage device or other peer storage devices, see figure 3 and paragraph 67, lines 10-13), to read data into a memory device configured outside of the memory sub-system from the logical block address in the storage space (remotely addressable memory 306, see figure 3 and paragraph 42, lines 7-9).
Lin’771, Sehgal’742, and Hahn’518 are analogous because they are both drawn to the same inventive field of storage configuration.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the sub-system of Lin’771 to include the memory device configured outside of the memory system by including the remotely addressable memory of Hahn’518.
The motivation for doing so would have been to enable a group of data storage devices, such as SSDs, to manage RAID configuration and control without using host or intermediate resources other than a peer-to-peer communication channel (paragraph 4).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 8, Lin’771 and Sehgal’742 do not appear to explicitly teach the memory sub-system of claim 7, further comprising: a direct memory access (DMA) engine configured to store data over the connection to the memory device.
However, Hahn’518 teaches a direct memory access (DMA) engine configured to store data over the connection to the memory device (remote DMA interface 304, see figure 3 and paragraph 40, line 3).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the sub-system of Lin’771 to include the DMA engine of Hahn’518 by incorporating a remote DMA interface into the system.
The motivation for doing so would have been to enable a group of data storage devices, such as SSDs, to manage RAID configuration and control without using host or intermediate resources other than a peer-to-peer communication channel (paragraph 4).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 10, Lin’771 and Sehgal’742 do not appear to explicitly teach wherein execution of the storage access request in the memory sub-system includes reading from or writing to the logical block address a data block but includes no communication of any portion of the data block between the host system and the memory sub-system.
However, Hahn’518 teaches wherein execution of the storage access request in the memory sub-system includes reading from or writing to the logical block address a data block but includes no communication of any portion of the data block between the host system and the memory sub-system (peer communication module 326 may include interfaces, functions, parameters, and/or data structures for providing communication among storage devices 120 using interconnect fabric 114 without being routed through storage controller 110 or another host or controller component, see figure 3 and paragraph 66, lines 1-6).
Prior to the effective filing date of the claim, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the method of Lin’771 to include the read/write without communication with the host by incorporating a peer communication module as disclosed by Hahn’518 to communicate among the storage devices.
The motivation for doing so would have been to enable a group of data storage devices, such as SSDs, to manage RAID configuration and control without using host or intermediate resources other than a peer-to-peer communication channel (paragraph 4).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 11, Lin’771 teaches the method of claim 10, wherein the storage access request includes a memory address in the memory space of the memory sub-system (host device 50 may send a plurality of host commands and a plurality of corresponding logic addresses to the memory controller 110, see figure 1 and paragraph 55, lines 1-2).
As to claim 14, Lin’771 does not appear to explicitly teach the method of claim 11, wherein the storage access protocol is in accordance with a standard for non-volatile memory express (NVMe).
However, Sehgal’742 teaches wherein the storage access protocol is in accordance with a standard for non-volatile memory express (NVMe) (use of the NVMe protocol over the CXL.io protocol, paragraph 54, lines 4-5).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the system of Lin’771 to include an NVMe-compliant storage access protocol by implementing the NVMe protocol over a CXL.io protocol.
The motivation for doing so would have been that the NVMe protocol is a commonly known protocol in the art of storage media, and that it would not have involved undue experimentation, nor would it have produced undesirable results.
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 15, Lin’771 teaches the method of claim 14, wherein the storage access protocol is in accordance with a standard for compute express link (CXL) or a standard for peripheral component interconnect express (PCIe, paragraph 54, line 13).
Sehgal’742 also teaches wherein the storage access protocol is in accordance with a standard for compute express link (CXL) or a standard for peripheral component interconnect express (use of the NVMe protocol over the CXL.io protocol, paragraph 54, lines 4-5; bus 407 may be a PCIe bus, see figure 4A and paragraph 27, lines 2-3).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the system of Lin’771 to include a storage access protocol in accordance with a CXL standard by implementing the NVMe protocol over a CXL.io protocol.
The motivation for doing so would have been that the CXL protocol is a commonly known protocol in the art of storage media, and that it would not have involved undue experimentation, nor would it have produced undesirable results.
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 16, Lin’771 does not appear to explicitly teach the method of claim 11, wherein the receiving of the storage access request includes receiving one or more memory access requests over the connection to store the storage access request in a submission queue configured in the memory space of the memory sub-system.
However, Sehgal’742 teaches wherein the receiving of the storage access request includes receiving one or more memory access requests over the connection (the host 110 generates an NVMe read command 530, see figure 5, block 580 and paragraph 42, lines 1-2) to store the storage access request in a submission queue (NoC driver 405 puts the CXL.io packet 435 with the wrapped NVMe write command 530 into the SQ 415, see figure 5, block 584 and paragraph 43, lines 3-5) configured in the memory space of the memory sub-system (DRAM 410 may set aside or reserve memory for a submission queue (SQ) 415, see figure 4A and paragraph 27, lines 7-9).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the method of Lin’771 to include the queue of Sehgal’742 by incorporating a command queue into the system.
The motivation for doing so would have been cost reductions in terms of using a single, common controller for both dynamic memory storage and non-volatile memory storage (paragraph 5, lines 7-9).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 17, Lin’771 does not appear to explicitly teach the method of claim 16, wherein the providing of the completion record includes storing, via one or more memory access requests over the connection, the completion record in a completion queue configured in the host system and outside of the memory sub-system.
However, Sehgal’742 teaches storing, via one or more memory access requests over the connection (the device controller 203 sends to the CQ 420 a signal that a status for the NVMe read command 530 should be updated to indicate completion of the command, see figure 5, block 596 and paragraph 45, lines 8-11), the completion record in a completion queue (completion queue 420, see figure 4A and paragraph 27, lines 7-9).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the method of Lin’771 to include the queue of Sehgal’742 by incorporating a completion queue into the system.
The motivation for doing so would have been cost reductions in terms of using a single, common controller for both dynamic memory storage and non-volatile memory storage (paragraph 5, lines 7-9).
Further, Hahn’518 teaches wherein the providing of the completion record includes storing, via one or more memory access requests over the connection, the completion record in a completion queue configured in the host system and outside of the memory sub-system (upon completion of each new RAID stripe, the RAID mapping table entries for that new RAID stripe may be replicated to the backup RAID mapping table over the peer communication channel, paragraph 63, lines 15-18).
Prior to the effective filing date of the claimed application, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the method of Lin’771 to include the completion record by having RAID mapping table entries replicated to a backup mapping table upon completion.
The motivation for doing so would have been to enable a group of data storage devices, such as SSDs, to manage RAID configuration and control without using host or intermediate resources other than a peer-to-peer communication channel (paragraph 4).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
As to claim 20, Lin’771 and Sehgal’742 do not appear to explicitly teach the non-transitory computer storage medium of claim 18, wherein the method further comprises: executing a further storage access request, received from the host system according to the storage access protocol, to write further data available in a memory device configured outside of the memory sub-system to a logical block address in the storage space, including retrieving, using a memory access protocol over the connection, the further data from the memory device according to a memory address identified in the further storage access request.
However, Hahn’518 teaches executing a further storage access request, received from the host system according to the storage access protocol (other distributed operations may use space in remotely addressable memory 306 as requested by the master storage device or other peer storage devices, see figure 3 and paragraph 67, lines 10-13), to write further data available in a memory device configured outside of the memory sub-system to a logical block address in the storage space (remotely addressable memory 306, see figure 3 and paragraph 42, lines 7-9), including retrieving, using a memory access protocol over the connection, the further data from the memory device according to a memory address identified in the further storage access request (peer communication module 326 may enable drive-to-drive messaging addressed by storage device identifiers, see figure 3 and paragraph 66, lines 6-10).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Lin’771, Sehgal’742, and Hahn’518 before them, to modify the method of Lin’771 to include the memory device configured outside of the memory system by including the remotely addressable memory of Hahn’518.
The motivation for doing so would have been to enable a group of data storage devices, such as SSDs, to manage RAID configuration and control without using host or intermediate resources other than a peer-to-peer communication channel (paragraph 4).
Therefore, it would have been obvious to combine Lin’771, Sehgal’742, and Hahn’518 to bring about the invention as claimed.
Allowable Subject Matter
Claims 6 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 6, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest the memory sub-system of claim 5, further comprising: an error correction code circuit configured to generate codewords for storing data in the non-volatile memory cells, where a size of each of the codewords is larger than a size of data at each of the plurality of memory addresses in the memory space.
Further, it would not have been obvious to combine the above-emphasized limitations with the remaining limitations of the claim.
Tzafrir (US 2017/0031845) discloses wherein controller is configured to send data (e.g., one or more ECC codewords generated by the ECC engine) and a write command to cause the memory device to store the data to a specified address of the memory. However, this reference does not appear to anticipate or explicitly teach the subject matter determined to be allowable.
As to claim 12, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest the method of claim 11, wherein the storage access request includes an opcode configured to cause the memory sub-system to read the data block from the logical block address; and the responding includes providing a portion of the data block read from the logical block address via the execution of the storage access request.
Further, it would not have been obvious to combine the above-emphasized limitations with the remaining limitations of the claim.
Hamilton (KR 20200102527) discloses wherein stored identification may be used by the controller to provide an indication (e.g., an opcode) that causes the memory device to perform a particular type of read operation for read requests that are subsequently received. However, this reference does not appear to anticipate or explicitly teach the subject matter determined to be allowable.
Note that claim 13 contains similarly allowable subject matter to that of claim 12 as shown above; therefore, it is determined to contain allowable subject matter by the same reasoning accordingly.
Response to Arguments
Applicant’s arguments, see “Rejections under 35 U.S.C. 102 and 103”, filed July 8, 2026, with respect to the rejection(s) of claim(s) 1-5, 7-11, and 14-20 under Lin and Hahn have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the Sehgal reference disclosed in an Information Disclosure Statement submitted on July 15, 2026, with an accompanying fee.
The current rejections are believed to have addressed any issues put forth in the arguments regarding the rejections. Therefore, for the sake of brevity, they are not repeated here.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tzafrir (US 2017/0031845) discloses wherein controller is configured to send data (e.g., one or more ECC codewords generated by the ECC engine) and a write command to cause the memory device to store the data to a specified address of the memory.
Hamilton (KR 20200102527) discloses wherein stored identification may be used by the controller to provide an indication (e.g., an opcode) that causes the memory device to perform a particular type of read operation for read requests that are subsequently received.
However, these references do not appear to anticipate or explicitly teach the subject matter determined to be allowable.
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on July 15, 2026, prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
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/J.B.R/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
