Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to application filed on 1/2/2025. Claims 1-20 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6, 8, 12-13, 15 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by AHN et al., US 2009/0089501 A1.
Regarding claims 1, 8 and 15, AHN teaches a method comprising:
receiving a first read command including a first logical block address (LBA) (section 0009;0012; and Fig.1);
determining that the first LBA and a first stored LBA in a cache share a spatial locality (section 0009 and 0047; A hard disk drive performs prefetching when a determination is made that a request of the host has a spatial locality), wherein the first LBA and the first stored LBA share a spatial locality when the first LBA is within a predetermined number of LBAs from the first stored LBA (section 0013; when a predetermined LBA store command is received from the external apparatus, storing the LBA in the non-volatile cache, and storing the LBA in the history of the non-volatile cache; section 0047);
removing the first stored LBA from the cache in response to the determination (section 0019; section 0039; storing one or more logical block addresses (LBAs) in the non-volatile cache, removing the one or more stored LBAs from the non-volatile cache, and checking a list of the one or more stored LBAs in the non-volatile cache); and
adding the first LBA to the cache (section 0039; a command used to store a LBA in the non-volatile cache 322 is "ADD LBA(S) TO NV CACHE PINNED SET DMA EXT" (hereinafter, referred to as an ADD LBA command). The ADD LBA command transmitted from the external apparatus 310 to the hard disk drive 320 includes information about interconnectivity of LBAs. That is, the external apparatus 310 stores LBAs having similar purposes in the non-volatile cache 322 through at least one continuous ADD LBA command).
Regarding claims 5 and 12, AHN teaches each stored LBA in the cache is paired with an access pattern (section 0009; the hard disk drive performs prefetching when data, which is requested to be read by the host, i.e. sectors have continuous logical block addresses (LBAs), and when a number of sectors is equal to or greater than a predetermined number. Data that is to be prefetched is also determined based on a spatial locality. That is, continuous pieces of data in the last LBA that is requested to be read by the host are read and stored in the buffer).
Regarding claims 6, 13 and 19, AHN teaches further comprising: receiving a read command including a second LBA; determining that the second LBA and the first stored LBA in the cache share the spatial locality; determining that the second LBA and a second stored LBA in the cache share the spatial locality; and mapping the second LBA to the second stored LBA using a first thread access pattern (Fig.1; section 0031; When the buffer 321 is used as a read buffer, the buffer 321 stores data that is transmitted to the external apparatus 310, and when the same data is requested to be read, the data is read from the buffer 321 instead of a hard disk 323. When the buffer 321 is used as a prefetch buffer, data that is expected to be requested by the external apparatus 310 in the near future is pre-read from the hard disk 323 or a non-volatile cache 322, and stored in the buffer 321. When the external apparatus 310 requests such stored data, the data can be quickly read from the buffer 321).
Allowable Subject Matter
Claims 2-4, 7, 9-11, 14, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the cache is a first-in-first-out (FIFO) cache, the method further comprising: receiving a second read command including a second LBA; determining a difference between the second LBA and each stored LBA in the FIFO cache; responsive to determining that the difference between the second LBA and each stored LBA in the FIFO cache does not satisfy a threshold, removing an oldest stored LBA in the FIFO cache; and adding the second LBA to the FIFO cache in combination with the other claimed limitations as described in the claims 2, 9 and 16 (claims 3, 10 and 17 are depended on claims 2, 9 and 16 respectively).
The limitations not found in the prior art of record include the cache is a first-in-first-out (FIFO) cache, the method further comprising: receiving a second read command including a second LBA; determining a difference between the second LBA and each stored LBA in the FIFO cache; responsive to determining that the difference between the second LBA and the first stored LBA in the FIFO cache satisfies a threshold range and the difference between the second LBA and a second stored LBA in the FIFO cache satisfies the threshold range, removing the first stored LBA from the FIFO cache and removing the second stored LBA from the FIFO cache; and adding the second LBA to the cache in combination with the other claimed limitations as described in the claims 4, 11 and 18.
The limitations not found in the prior art of record include mapping the second LBA to the second stored LBA using the first thread access pattern further comprises: determining the first thread access pattern by combining a weighted average of a plurality of stride sizes of a plurality of read commands to obtain an expected LBA issued by a first thread; and matching the expected LBA to the second LBA in combination with the other claimed limitations as described in the claims 7, 14 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Basso et al., US 2023/0195474 A1 teaches a memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
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/HUA J SONG/Primary Examiner, Art Unit 2133