DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8-9, 11-12, 14-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pala et al. (20250202474).
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With respect to claim 1, figure 1C of Pala et al. (20250202474) produces a method for enhancing controllability on switching speed of an electronic cascode power device comprising a high-voltage normally-ON transistor (J1) having a drain connected to the high-side terminal (N1) of the cascode power device (see [0045], “[0045] Although the cascode switch device of FIGS. 2-6, and the power switch device of FIG. 8 only shows a serially connected normally-on switch device and a normally-off switch device. However, the present disclosure is not limited thereto. The cascode switch device may have one or more resistors, capacitors and other components and circuits coupled to the source, gate, or drain terminal of the normally-on switch device or the normally-off switch device.”) and a gate connected to the low-side terminal (N2) and a low-voltage normally-OFF transistor (M1) having a drain connected to a source of the high-voltage normally-ON transistor, a source connected to the low-side terminal of the cascode power device (at N2) and a gate connected to the control terminal of the cascode power device (at 26/ SD); the method comprises introducing a coupling capacitor (GDM) into the electronic cascode power device by: connecting a first terminal (between CGSJ and CGDM) of the coupling capacitor to the source of the high-voltage normally-ON transistor; and connecting a second terminal (at 26) of the coupling capacitor to the gate of the low-voltage normally-OFF transistor.
With respect to claim 2, Pala et al. discloses the method of claim 1, wherein the high-voltage normally-ON transistor is a SiC junction-gate field-effect transistor. (See [0002], “The normally-on switch device is a high-voltage transistor (HVT), e.g., a SiC/GaN JFET”)
With respect to claim 4, Pala et al. discloses the method of claim 2, wherein the low-voltage normally-OFF transistor is a Si metal- oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 5, Pala et al. discloses the method of claim 1, wherein the high-voltage normally-ON transistor is a GaN high- electrol-mobility transistor. (See [0002], “The normally-on switch device is a high-voltage transistor (HVT), e.g., a SiC/GaN JFET”)
With respect to claim 6, Pala et al. discloses the method of claim 5, wherein the low-voltage normally-OFF transistor is a Si metal- oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 8, Pala et al. discloses the method of claim 1, wherein the low-voltage normally-OFF transistor is a Si metal- oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 9, Pala et al. discloses the method of claim 1, wherein the coupling capacitor is a discrete component or monolithically integrated with the low-voltage normally-OFF transistor. (discrete)
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With respect to claim 11, figure 1C of Pala et al. (20250202474) discloses an electronic cascode power device with enhanced controllability on switching speed, comprising: a high-voltage normally-ON transistor (J1) having a drain connected to the high-side terminal of the cascode power device (at N1) and a gate connected to a low-side terminal of the cascode power device (at N2); a low-voltage normally-OFF transistor (M1) having a drain connected to a source of the high- voltage normally-ON transistor, (at N2) a source connected to the low-side terminal of the cascode power device and a gate connected to a control terminal of the cascode power device (via capacitors); and a capacitor (GDM) having a first terminal connected to the source of the high-voltage normally- ON transistor (J1) and a second terminal connected to the gate (at 26/ SD) of the low-voltage normally-OFF transistor. (See [0027] “The JFET J1 is a high voltage normally-on (depletion mode) device, while the Si MOSFET M1 is a low voltage normally-off (enhancement mode) device.”)
With respect to claim 12, Pala et al. discloses the electronic cascode power device of claim 11, wherein the high-voltage normally- ON transistor is a SiC junction-gate field-effect transistor. (See [0002], “The normally-on switch device is a high-voltage transistor (HVT), e.g., a SiC/GaN JFET”)
With respect to claim 14, Pala et al. discloses the electronic cascode power device of claim 12, wherein the low-voltage normally- OFF transistor is a Si metal-oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 15, Pala et al. discloses the electronic cascode power device of claim 11, wherein the high-voltage normally- ON transistor is a GaN high-electrol-mobility transistor. (See [0002], “The normally-on switch device is a high-voltage transistor (HVT), e.g., a SiC/GaN JFET”)
With respect to claim 16, Pala et al. discloses the electronic cascode power device of claim 15, wherein the low-voltage normally- OFF transistor is a Si metal-oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 18, Pala et al. discloses the electronic cascode power device of claim 11, wherein the low-voltage normally- OFF transistor is a Si metal-oxide-semiconductor field-effect transistor. (See [0002], “The normally-off switch device is a low-voltage transistor (LVT), e.g., a Si MOSFET.”)
With respect to claim 19, Pala et al. discloses the electronic cascode power device of claim 11, wherein the coupling capacitor is a discrete component or monolithically integrated with the low-voltage normally-OFF transistor. (discrete component).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 7,10 13, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pala et al. (20250202474).
With respect to claim 3, Pala et al. teaches the method of claim 2, but fails to disclose wherein the low-voltage normally-OFF transistor is a GaN high-electrol-mobility transistor.
It is well known in the art to interchange low voltage normally off Silicon MOSFETs for GaN high electrol mobility transistors. It would have been obvious before the effective filing date of the claimed invention to exchange the LV normally off Silicion MOSFET in Pala et al. for a GaN for the purpose GaN HEMTs are well suited for high-efficiency, high speed switching, as at low voltages, GaN HEMTs offer better efficiency and speed than Si MOSFETs for power switching.
With respect to claim 7, the combination/teaching above discloses the method of claim 1, wherein the low-voltage normally-OFF transistor is a GaN high-electrol-mobility transistor.
With respect to claim 10, Pala et al. discloses the method of claim 1, but fails to disclose wherein the coupling capacitor has a capacitance value in a range of 1 to 2000 pF. The range of 1 to 2000pF is deemed a ‘result-effective variable’ as no reason for the range is stated in the disclosure. However, a capacitance around the range of 1000pF is well known in the art as it si suitable for high-frequency gate drive, the capacitance may be used to match the switching frequency from optimization and where small capacitors around the range of 1000pF are suited to handle fast transients and gate drives.
It would have been obvious before the effective filing date of the claimed invention to use a capacitor of around 1000pF in a Cascode power supply switching device for the purpose of optimal performance.
With respect to claim 13, Pala et al. discloses the electronic cascode power device of claim 12, but fails to disclose wherein the low-voltage normally-OFF transistor is a GaN high-electrol-mobility transistor.
It is well known in the art to interchange low voltage normally off Silicon MOSFETs for GaN high electrol mobility transistors. It would have been obvious before the effective filing date of the claimed invention to exchange the LV normally off Silicion MOSFET in Pala et al. for a GaN for the purpose GaN HEMTs are well suited for high-efficiency, high speed switching, as at low voltages, GaN HEMTs offer better efficiency and speed than Si MOSFETs for power switching.
With respect to claim 17, the teaching/combination above produces the electronic cascode power device of claim 11, but fails to disclose wherein the low-voltage normally- OFF transistor is a GaN high-electrol-mnobility transistor.
It is well known in the art to interchange low voltage normally off Silicon MOSFETs for GaN high electrol mobility transistors. It would have been obvious before the effective filing date of the claimed invention to exchange the LV normally off Silicion MOSFET in Pala et al. for a GaN for the purpose GaN HEMTs are well suited for high-efficiency, high speed switching, as at low voltages, GaN HEMTs offer better efficiency and speed than Si MOSFETs for power switching.
With respect to claim 20, Pala el al. discloses the electronic cascode power device of claim 11, but fails to disclose wherein the coupling capacitor has a capacitance value in a range of 1 to 2000 pF. The range of 1 to 2000pF is deemed a ‘result-effective variable’ as no reason for the range is stated in the disclosure. However, a capacitance around the range of 1000pF is well known in the art as it si suitable for high-frequency gate drive, the capacitance may be used to match the switching frequency from optimization and where small capacitors around the range of 1000pF are suited to handle fast transients and gate drives.
It would have been obvious before the effective filing date of the claimed invention to use a capacitor of around 1000pF in a Cascode power supply switching device for the purpose of optimal performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00).
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/KHAREEM E ALMO/Examiner, Art Unit 2836
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