DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-3, 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ryczek (USPN 4513343).
Regarding claim 1, Ryczek discloses an electronic device (an electronic device 2, see figures 1, 4) with a short circuit protection function (a short circuit protection function performed by a short circuit protector 18), the electronic device comprising:
a first switch (such as a switch includes Q2-Q3 of figure 4) disposed between an output node (an output node T1) and an electronic component (an electronic component 14), wherein a power converter (a power converter RB) provides an output voltage to the output node (T1), and a circuit (a circuit 10) is connected to the output node;
a detection circuit (a detection circuit includes D1, C1, R6, R7) configured to detect whether or not a short circuit failure occurs in the electronic component (the component 14) (an excess current flows through the component 14 when a short circuit fault detected, see col. 2, lines 39-40, lines 49-53); and
a second switch (a second switch Q4) connected to a first control terminal of the first switch (a base terminal of the Q2-Q3), wherein the second switch (Q4) is configured to determine whether to control the first switch (Q2-Q3) to be turned off or turned on according to a detection result of the detection circuit (the switch Q2-Q3 is turned off in response to the short circuit fault and turned on when the short circuit fault when there is no short circuit fault);
wherein, in response to the detection circuit detecting that the short circuit failure occurs in the electronic component (14), the second switch (Q4) is used to control the first switch (Q2-Q3) to be turned off, and in response to the detection circuit detecting that the short circuit failure does not occur in the electronic component (14) , the second switch (Q4) is used to control the first switch to be turned on (such as the Q2-Q3 provides a low impedance path when there is no short circuit fault detected) (see col. 2, lines 39-40, lines 49-53, lines 64-68, col. 4, lines 28-51).
Regarding claim 2, Ryczek discloses wherein the first switch (Q2-Q3) further has a first terminal (the collector terminal of Q3) connected to the output node (T1) and a second terminal (emitter terminal) connected to the electronic component (14), and the electronic component (14) is connected between the second end of the first switch and a ground terminal (the terminal T2 of a DC voltage provides a zero voltage reference and considered as a ground terminal).
Regarding claim 3, Ryczek discloses wherein the second switch (Q4) has a first terminal (the collector terminal of Q4) connected to the first control terminal (the base of Q2-Q3), a second terminal (emitter terminal of Q4) connected to the ground terminal (T2), and a second control (a base terminal of Q4) terminal connected to the detection circuit.
Regarding claim 14, Ryczek discloses wherein the first switch (Q3) and the second switch (Q4) are each a metal-oxide-semiconductor field-effect transistor or a bipolar junction transistor (the Q3, Q4 are bipolar transistors) (see figure 4).
Allowable Subject Matter
2. Claims 4-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANNY NGUYEN/ Primary Examiner, Art Unit 2838
Prosecution Insights