DETAILED ACTION
This Office action is in response to the application filed on 03 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 4 is objected to because of the following informalities: Second-to-last line of claim 4, “the second phase” should be changed to “the third phase” as this is the phase, as defined in claim 3 and shown in Fig. 4C of the specification, in which the second capacitor is in parallel to the first capacitor. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 12 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fu et al. (US Patent 9,641,0981; hereinafter “Fu”).
In re claim 1, Fu discloses a switching regulator circuit (Figs. 1, 2) comprising:
a converting stage (108) including a first switch (Q1) connected between an input node (node labeled E/2) to which an input voltage (E/2) is applied and a first node (node between Q1/Q2/Q8), a second switch (Q2) connected between the first node and a second node (node Va), a third switch (Q3) connected between the second node and a third node (node between Q3/Q4/Q6), a fourth switch (Q4) connected between the third node and a fourth node (node labeled -E/2), a first capacitor (C3) connected between the first node and the third node, and an inductor (Lo) connected between the second node and an output node (node Vo);
an input stage (102) including a second capacitor (C1) connected between the input node and a fifth node (ground-labeled node) and a third capacitor (C2) connected between the fifth node and the fourth node; and
a balancing control stage (104, 106) connected to the input stage (102) and the converting stage (108) and configured to control balancing of a voltage of the first capacitor (col. 11: 35-46).
In re claim 2, Fu discloses wherein the balancing control stage (104, 106) includes:
a fifth switch (106) connected between the fifth node and the first node; and
a sixth switch (104) connected between the fifth node and the third node.
In re claim 3, Fu discloses wherein, during a first phase, the second switch, the fourth switch and the fifth switch are configured to be turned on (see switch status table of Fig. 2: Mode 1 with Va=-E/4 has switches Q2, Q4, and Q7 turned on),
during a second phase, the third switch and the fourth switch are configured to be turned on or the first switch and the second switch are configured to be turned on (id.: Mode 1 with Va=E/2 has switches Q1 and Q2 turned on; Mode 1 with Va=-E/2 has switches Q3 and Q4 turned on),
during a third phase, the first switch, the third switch, and the sixth switch are configured to be turned on (id.: Mode 1 with Va=E/4 has switches Q1, Q3 and Q5 turned on), and
during a fourth phase, the third switch and the fourth switch are configured to be turned on or the first switch and the second switch are configured to be turned on (see note for second phase, above).
In re claim 4, Fu discloses wherein, during the first phase, the third capacitor is connected in parallel to the first capacitor and configured to compensate for the voltage of the first capacitor (Fig. 2: Mode 1 with Va=-E/4 has switches Q2, Q4, and Q7 turned on; thus C2 is connected parallel to C3 through switches Q7/D8 and Q4), and during the
In re claim 12, Fu discloses a switching regulator circuit (Figs. 1, 2) comprising:
a multi-level converting stage (108 and C3) including a flying capacitor (C3) and configured to step down an input voltage (E) applied through an input node (positive electrode of source E) to generate an output voltage (Vo);
a plurality of decoupling capacitors (C1, C2) connected in series to the input node (C1 and C2 are connected in series from the input node) and configured to stabilize the input voltage (this is understood to be the inherent function of C1, C2 based on the known, transient behavior of capacitors connected across a DC link); and
a balancing control stage (104, 106) including a plurality of balancing switches (104, 106) connected to both terminals of the flying capacitor (C3) and the plurality of decoupling capacitors (C1, C2) and configured to control voltage balancing of the flying capacitor by connecting the plurality of decoupling capacitors to the flying capacitor (col. 11: 35-46).
In re claim 18, Fu discloses a power supply circuit (Figs. 1, 2) comprising:
a converting circuit (100) configured to step down an input voltage (E) through a switching operation of a plurality of switches (Q1-Q4) to generate an output voltage (Vo; see Fig. 2: positive output voltages include E/2 or E/4); and
a switching control circuit (see Fig. 20) configured to generate switching signals (signals Q1-Q8) that control a switching operation of the plurality of switches based on a voltage level of the output voltage (col. 14: 13-44 describe general functionality of the control circuit Fig. 20), wherein the converting circuit includes:
a 3-level buck converting stage (108, C3, Lo) including a plurality of converting switches (Q1-Q4) to which the input voltage (E) is applied, a flying capacitor (C3), and an inductor (Lo);
a plurality of decoupling capacitors (C1, C2) connected in series to an input node (positive electrode of source E) and configured to stabilize the input voltage (this is understood to be the inherent function of C1, C2 based on the known, transient behavior of capacitors connected across a DC link); and
a balancing control stage (104, 106) including a plurality of balancing switches (104, 106) connected to both terminals of the flying capacitor (C3) and the plurality of decoupling capacitors (C1, C2) and configured to control balancing of a voltage of the flying capacitor by connecting, in response to the plurality of converting switches performing a switching operation, the plurality of decoupling capacitor to the flying capacitor (col. 11: 35-46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fu in view of Hoyerby (US Patent 10,063,1472).
In re claim 13, Fu discloses wherein the multi-level converting stage (see Fig. 1) further includes:
a second switch (Q2) connected between a first node (node between Q1/Q2/Q8) and a second node (node Va);
a third switch (Q3) connected between the second node and a third node (node between Q3/Q4/Q6);
a fourth switch (Q4) connected between the third node and a fourth node (node -E/2);
an inductor (Lo) connected between the second node and an output node (node Vo); and
a stabilizing capacitor (Co) connected to the output node,
wherein the flying capacitor (C3) is connected between the first node and the third node (see Fig. 1).
Fu does not disclose that a ground voltage is applied to the fourth node (in Fu, ground is applied to the neutral point between C1 and C2 as shown). However, Hoyerby discloses a similar multi-level, flying capacitor converter (Fig. 2) and demonstrates that ground could alternatively be applied to the fourth node at the drain of the fourth switch (201), in order for the converter to be configured to function as a DC-DC converter, for instance for producing multiple DC outputs connecting to a subsequent DC-AC inverter stage (see Abstract, col. 8: 28-60).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter of Fu by applying a ground voltage to the fourth node as shown by Hoyerby in order to operate the circuit as a DC-DC converter stage producing multiple DC outputs for subsequent conversion to AC.
In re claim 14, Fu as modified discloses wherein the plurality of decoupling capacitors include (see Fig. 1): a first decoupling capacitor (C1) and a second decoupling capacitor (C2). Fu does not explicitly disclose third and fourth decoupling capacitors, with the first-fourth decoupling capacitors all connected as recited in claim 14.
However, Fu implies or suggests (col. 5: 26-38) an alternative embodiment including additional decoupling capacitors for the purpose of achieving an output staircase waveform having additional voltage levels. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Fu by including additional third and fourth decoupling capacitors, with the result that the plurality of decoupling capacitors include: a first decoupling capacitor connected between the input node and a sixth node; a second decoupling capacitor connected between the sixth node and a fifth node; a third decoupling capacitor connected between the fifth node and a seventh node; and a fourth decoupling capacitor connected between the seventh node and the fourth node, for the stated purpose of enabling additional output voltage levels.
Allowable Subject Matter
Claims 5-11, 15-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, the closest prior art in Fu discloses the invention according to claim 2 as explained above, but does not further disclose wherein sizes of the fifth switch and the sixth switch are 0.1 times or less than sizes of the first switch, the second switch, the third switch, and the fourth switch. Rather, Fu is silent as to the relative sizes of the switches. Furthermore, the additional prior art on record does not suggest to configure the switches to be sized in the manner recited in the claim.
With respect to claim 6, the closest prior art in Fu discloses the invention according to claim 4 as explained above. Further, while Fu does not explicitly disclose the input stage including a fourth and fifth capacitor, this was demonstrated to be an obvious modification in light of the suggestion of just such an embodiment by Fu (see rejection of claim 14, above). However, even after such modification, the converter in Fu would still lack a seventh switch connected between the first node and the sixth node; and an eighth switch connected between the third node and the seventh node as recited in claim 6.
Furthermore, the additional prior art on record does not suggest a balancing circuit with seventh and eight switches connected among four decoupling capacitors of an input stage in the manner claimed.
Claims 7-11 each depend, either directly or indirectly, from claim 6 and thus would be allowable for the same reasons.
With respect to claim 15, the combination of Fu and Hoyerby discloses the invention according to claim 14 as explained above, but does not further disclose wherein the balancing control stage is configured to connect the first decoupling capacitor and the second decoupling capacitor to a first terminal of the flying capacitor or connect the third decoupling capacitor and the fourth decoupling capacitor to a second terminal of the flying capacitor, in a first mode, and the balancing control stage is configured to connect the first decoupling capacitor to the first terminal of the flying capacitor and connect the fourth decoupling capacitor to the second terminal of the flying capacitor, in a second mode. That is, Fu only suggests the possibility of additional capacitors, but does not specifically teach how the balancing circuit would function in such an embodiment, and the functional limitations of claim 15 are not apparently obvious in light of the prior art on record as a whole.
Claims 16 and 17 each depend from claim 15 and thus would be allowable for the same reasons.
With respect to claim 19, the closest prior art in Fu discloses the invention according to claim 18 as explained above. Further, while Fu does not explicitly disclose the input stage including third and fourth decoupling capacitors, this was demonstrated to be an obvious modification in light of the suggestion of just such an embodiment by Fu (see rejection of claim 14, above). However, even after such modification, the converter in Fu would still lack the functional limitations concerning the operation of the balancing stage with respect to the four decoupling capacitors, for similar reasons as explained above with respect to claim 15.
Claim 20 depends from claim 19 and thus would be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2013/0270917 discloses a MULTILEVEL POWER CONVERTER having a balancing stage coupled between input decoupling capacitors and a flying capacitor.
US 2016/0043659 discloses a MULTILEVEL CONVERTER having a balancing stage coupled between input decoupling capacitors and a flying capacitor.
US 2018/0309383 discloses a Five-Level Inverter Topology With High Voltage Utilization Ratio.
US 2018/0062537 a Hybrid Modulation Strategy For Multilevel Inverters including four decoupling capacitors but without a flying capacitor.
WO 2023/031346 discloses a FLYING CAPACITOR CONVERTER WITH VOLTAGE BALANCING CIRCUIT.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 Previously cited by Applicant in an Information Disclosure Statement.
2 Previously cited by Applicant in an Information Disclosure Statement.
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