DETAILED ACTION
This is in response to communication filed on August 10, 2026.
Status of Claims
Claims 1 – 21 are pending, of which claims 1, 8, and 15 are in independent form.
Drawings
The drawings are objected to because Fig. 6 step 615 still states ‘decode, the decode circuitry, the encoded vdecode the encoded XOR3PP instruction.’ Again, the examiner believes that this phrase contains a typo, since the phrase refers to decoding “the encoded vdecode the encoded XOR3PP instruction.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
In light of applicant’s amendments to the specification, the examiner withdraws the previous objection to the specification.
Claim Rejections - 35 USC § 112
In light of applicant’s amendments to the claims, the examiner withdraws the previous rejection to the claims under 35 USC 112.
Claim Objections
In light of applicant’s amendments to the claims, the examiner withdraws the previous objection to the claims.
Double Patenting
In light of applicant’s statement regarding addressing double patenting once that claims are allowed, the previous double patenting rejection is maintained.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 6, 8 – 13, and 15 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wolrich et al., U.S. Patent Application 2014/0189369 (hereinafter referred to as Wolrich) in view of Rawat et al., ‘SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje’ (hereinafter referred to as Rawat).
Referring to claim 1, Wolrich discloses “A hardware processor, comprising: fetch circuitry to fetch” (Fig. 3 and [0065] - [0067] processor with instruction fetch unit) “an encoded instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register,” “wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value” (Fig. 9 and [0113] “SHA256_2RND” instruction, "The instruction specifies or otherwise indicates a first source 914, specifies or otherwise indicates a second source 916, specifies or otherwise indicates a third source 944, and specifies or otherwise indicates a destination 918); “decode circuitry to decode the encoded instruction to generate a decoded instruction” (Fig. 3 and [0065] - [0067] processor with decoder 313); “and execution circuitry to execute the decoded instruction” (Fig. 3 and [0065] – [0067] execution logic 312) “to: determine a first rotational value and a second rotational value” ([0075] processing of SHA2 round includes ai ROTR 2, ai ROTR 13, ai ROTR 22); “perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value” ([0075] processing of SHA2 round includes ai ROTR 2, ai ROTR 13, ai ROTR 22); “perform an exclusive OR (XOR) operation on at least a portion of the first value, at least a portion of the second value” ((a.sub.i ROTR 2) XOR (a.sub.i ROTR 13) XOR (a.sub.i ROTR 22)); “and store the” “XOR result” (Fig. 9 and [0113] destination register 918).
Wolrich does not appear to explicitly disclose “a fourth source identifier to identify a fourth operand.”
Also, Wolrich does not appear to explicitly disclose “perform an exclusive OR (XOR) operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.”
However, Rawat discloses more SHA instructions (Abstract and Introduction) including an instruction including another “source identifier to identify” another “operand” (section 4.2 immediate value as an operand, the immediate field contains the required rho offset value).
It would have been obvious to combine the teachings of Rawat’s operand for an immediate field containing rho offset values with the three operand instruction of Wolrich so that the immediate operand is a “fourth operand” and “a fourth source identifier to identify a fourth operand” is used in the instruction.
Rawat also discloses an instruction to “perform an exclusive OR (XOR) operation on at least a portion of the first value” “and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result” (section 2.2 describes Keccak steps theta includes rotate and XOR, rho includes rotate, X includes combining of bits of nearby lanes with AND, XOR, and NOT operations. Also see Fig. 4. section 4.1 with Figure 7 a) shows rotate a source data and XOR with another source data. section 4.2 with Figure 7 b) shows XOR two sources and rotate the result. These instructions accelerate calculations of Keccak by combining steps into a single instruction).
It would have been obvious to one of ordinary skill in the art to combine Rawat with Wolrich’s three operand instruction so that the instruction is to “perform an exclusive OR (XOR) operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result.”
Wolrich and Rawat are analogous art because they are from the same field of endeavor, which is SHA instructions.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Wolrich and Rawat before him or her, to modify the teachings of Wolrich to include the teachings of Rawat so that the instruction includes a fourth operand and the instruction performs an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result.
The motivation for doing so would have been to provide an instruction that combines theta, rho, and pi steps of Keccak in a single instruction (as described by Rawat at section 4.2).
Therefore, it would have been obvious to combine Rawat with Wolrich to obtain the invention as specified in the instant claim.
As per claim 2, Wolrich discloses “commit circuitry to commit a result of the executed instruction” (Fig. 17A and [0182] commit stage 1724).
As per claims 3 and 4, Wolrich discloses “the first register is a 512-bit register
that stores a 64-bit value” and “the first register stores eight 64-bit words” ([0006 SHA-512 with message digest of 512-bits, eight state words each 64-bits, [0161] "The 512-bit registers ZMM0 through ZMM31 are operable to hold 512-bit packed data, 256-bit packed data, and/or 128-bit packed data" "Different data element sizes are supported including" "64-bit quadword").
As per claim 5, Wolrich discloses “the operation is performed on all eight words” ([0009] eight state words are input to the round).
As per claim 6, neither Wolrich nor Rawat appears to explicitly disclose “the first rotational value and the second rotational value are based on a single bit in the fourth operand.”
However, as above, Rawat discloses “the first rotational value and the second rotational value” are based on bits “in the fourth operand” (section 4.2 immediate value as an operand, the immediate field contains the required rho offset value).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s invention to utilize any number of bits to convey a rotational value. In other words, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s invention to modify Wolrich/Rawat so that “the first rotational value and the second rotational value are based on a single bit in the fourth operand.”
A number of bits to represent a value is a design decision based on possible variants of the data, cost of extra bits, etc.
Referring to claim 8, claim 1 recites the corresponding limitations as that of claim 8. Therefore, the rejection of claim 1 applies to claim 8.
Note, claim 9 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 9.
Note, claim 10 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 10.
Note, claim 11 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 11.
Note, claim 12 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 12.
Note, claim 13 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 13.
Referring to claim 15, claim 1 recites the corresponding limitations as that of claim 15. Therefore, the rejection of claim 1 applies to claim 15.
Also, Wolrich discloses “A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to” carry out the steps of claim 1 (([0163] – [0164] machine-readable storage medium).
Note, claim 16 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 16.
Note, claim 17 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 17.
Note, claim 18 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 18.
Note, claim 19 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 19.
Note, claim 20 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 20.
Claims 7, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wolrich in view of Rawat, as applied to claims above, further in view of Wolrich et al., U.S. Patent Application 2014/0189368 (hereinafter referred to as Wolrich ‘368).
As per claim 7, Wolrich discloses “the first source, the second source, and
the third source are 512-bit long” and using “an 8-bit integer immediate” (Fig. 9 and [0113] "The instruction specifies or otherwise indicates a first source 914, specifies or otherwise indicates a second source 916, specifies or otherwise indicates a third source 944, and specifies or otherwise indicates a destination 918. [0006] SHA-512 with message digest of 512-bits, eight state words each 64-bits, [0161] "The 512-bit registers ZMM0 through ZMM31 are operable to hold 512-bit packed data, 256-bit packed data, and/or 128-bit packed data" [0169] IMM8 1572).
Neither Wolrich nor Rawat appears to explicitly disclose “the fourth source is an 8-bit integer immediate.”
However, Wolrich ‘368 discloses another instruction for SHA hashing wherein another “source is an 8-bit integer immediate” ([0043] rotate set specified by a field in an immediate operand. [0095] immediate byte).
It would have been obvious to combine the teachings of Wolrich ‘368 with the three operand instruction of Wolrich so that the immediate operand is a “fourth source.”
Wolrich, Rawat, and Wolrich ‘368 are analogous art because they are from the same field of endeavor, which is SHA instructions.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Wolrich, Rawat, and Wolrich ‘368 before him or her, to modify the teachings of Wolrich and Rawat to include the teachings of Wolrich ‘368 so that the immediate operand is a “fourth source.”
The motivation for doing so would have been to provide a flexible means for identifying input information (as described by Wolrich ‘368 at [0095]).
Therefore, it would have been obvious to combine Wolrich ‘368 with Wolrich and Rawat to obtain the invention as specified in the instant claim.
Note, claim 14 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 14.
Note, claim 21 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 21.
Response to Arguments
Applicant's arguments filed August 10, 2026 have been fully considered but they are not persuasive.
Applicant argues, on page 11 that
In the Office Action, the Examiner relies on Wolrich to teach a three-input XOR operation and relies on Rawat to teach a fourth operand with XOR and rotate operations. Wolrich, as cited, discloses a Sigma function (e.g., "(ai ROTR 2) XOR (ai ROTR 13) XOR (ai ROTR 22)") that is an XOR of a single value (ai) rotated by three different fixed amounts. Wolrich, as cited, does not appear to teach a three-input XOR of three distinct values (i.e., a first value, a second value, and a rotated third value). Furthermore, Rawat discloses a "kxorr64" instruction that performs a two-input XOR followed by a single rotate operation. Neither reference teaches or suggests a single instruction that performs a first rotate operation, a three-input XOR of distinct operands, and a second rotate operation of the XOR result, as required by claim 1.
The examiner disagrees. The previous office action cites Wolrich at Fig. 9 and [0113], which describes a three source instruction with SHA2 rounding. Applicant has not addressed this mapping of Wolrich when arguing that Wolrich “does not appear to teach a three-input XOR of three distinct values (i.e., a first value, a second value, and a rotated third value).” Wolrich shows first source 914, second source 916, and third source 944 in Fig. 9.
Further, the previous office action cites Rawat’s teaching of an immediate value as operand for a SHA instruction. The examiner’s position is that “It would have been obvious to combine the teachings of Rawat's operand for an immediate field containing rho offset values with the three operand instruction of Wolrich so that the immediate operand is a "fourth operand" and "a fourth source identifier to identify a fourth operand" is used in the instruction.” Applicant has not addressed this combination of the office action.
Further still, as in the previous office action, the examiner’s position is that “It would have been obvious to one of ordinary skill in the art to combine Rawat with Wolrich's three operand instruction SO that the instruction is to "perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result.”” Again, Applicant has not addressed this combination of the office action.
Applicant argues, on pages 11 - 12 that
“The Examiner has impermissibly reconstructed the claimed invention by piecing together isolated mathematical operations from different, incompatible cryptographic algorithms using hindsight derived from Applicant's own disclosure.
In addition, the proposed modification of Wolrich based on Rawat is improper because it would destroy the principle of operation of the primary reference.”
“Modifying the internal execution circuitry of the SHA-2 instruction of Wolrich to perform Keccak (SHA-3) specific steps (such as the theta, rho, and pi steps) appears to be incompatible with the instruction's ability to compute SHA-256 rounds.”
The examiner disagrees. Wolrich shows two source operand instructions with SHA2 processing as well as three source operand instructions with SHA2 processing. The examiner maintains that one of ordinary skill in the art would have found it obvious to combine Rawat’s teachings with Wolrich so that a fourth source is used in SHA processing. One of ordinary skill in the art would understand how to combine this idea of Rawat with the teachings of Wolrich into a new instruction that calculates Keccak steps with improved performance.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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