CTNF 19/009,066 CTNF 83896 DETAILED ACTION This is in response to the application filed on January 3, 2025 in which claims 1 – 21 are presented for examination. 12-151 AIA 26-51 12-51 Status of Claims Claims 1 – 21 are pending, of which claims 1, 8, and 15 are in independent form. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 2/5/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings 06-22 AIA The drawings are objected to because the replacement drawing page received January 3, 2025 has Fig. 6 using the acronym ‘XOR3P’ when the examiner believes that this acronym should read ‘XOR3PP.’ Further, Fig. 6 step 615 states ‘decode, by the decode circuitry, the encoded vdecode the encoded XOR3PP instruction.’ The examiner believes that this phrase contains a typo . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Applicant’s Abstract and Specification has the acronym ‘XOR3P’ in several instances. It seems that Applicant’s invention is an instruction that is correctly labeled ‘XOR3PP’ in most instances. The examiner recommends amending all instances of ‘XOR3P’ to be ‘XOR3PP.’ Applicant’s PGPub 2025/0138829 at [0048] describes Fig. 2C and states “At operation 214.” The examiner believes that this phrase should state “At operation 214 222 .” Applicant’s PGPub 2025/0138829 at [0054] describes “Referring to Fig. 2C” and states “two XOR3P operations.” The examiner recommends amending this paragraph to state “Referring to Fig. 2C 2D ” and states “two XOR3P XOR3PP operations.” Applicant’s PGPub 2025/0138829 at [0055] describes “Fig. 3A” twice. The examiner recommends amending each instance to state “Fig. 3A 3 .” Applicant’s PGPub 2025/0138829 at [0056] describes “register 310.” The examiner recommends amending this to state “register 310 410 .” Applicant’s PGPub 2025/0138829 at [0061] describes “registers and/or memory 508.” The examiner recommends amending this to state “ registers register file and/or memory 508 510 .” Applicant’s PGPub 2025/0138829 at [0062] describes “Exemplary detailed execution circuitry is shown in FIG. 2A-2E and FIG. 4A-4C.” The examiner recommends amending this to state “Exemplary detailed execution circuitry is operations are shown in FIG. 2A-2E and FIG. 4A-4C.” Applicant’s PGPub 2025/0138829 at [0068] describes “Comparing FIG. 6 to FIGS. 7A-C, first source identifier 606 in some embodiments of AVX instruction format, occupies the register index field 744, second source identifier 608 occupies the RIM field 746, and destination identifier 604 occupies the VEX.vvvv field 720.” The examiner recommends amending this to state “Comparing FIG. 6 to FIGS. 7A-C, a first source identifier 606 in some embodiments of AVX instruction format, occupies the register index field 744, a second source identifier 608 occupies the RIM field 746, and a destination identifier 604 occupies the VEX.vvvv field 720.” Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2 and 16 recite the limitation "the executed transform instruction" in line 2 of each claim. There is no previous mention of a ‘transform instruction’ in the claims. There is insufficient antecedent basis for this limitation in the claim. Claim Objections 07-29-01 AIA Claim s 1 – 21 are objected to because of the following informalities: Independent claims 1, 8, and 15 state ‘XOR3P instruction’ followed by several citations of ‘XOR3PP instruction.’ As above, the examiner believes that the proper instruction is ‘XOR3PP instruction.’ The remaining claims inherit this objection based on their dependencies . Appropriate correction is required. 07-29-01 AIA Claim s 1 – 21 are objected to because of the following informalities: Independent claims 1, 8, and 15 state ‘perform an XOR instruction’ without further definition for this acronym. The examiner suggests amending each independent claim to state ‘perform an exclusive OR ( XOR ) instruction.’ The remaining claims inherit this objection based on their dependencies . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim s 6, 13, and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 8, and 15 of copending Application No. 18/145776 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 6, 13, and 20 explain that the rotational values come from the fourth operand. Further, claims 6, 13, and 20 are different from claims 1, 8, and 15 of 18/145776 by stating ‘at least a portion of’ a value is rotated and XORed. Finally, the cited ‘first value’ is changed to ‘third value.’ However, naming a value first, second, or third does not provide a patentable difference. Also, ‘at least a portion’ includes cases of the full value . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 18/145776 19/009066 1. A hardware processor, comprising: fetch circuitry to fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decode circuitry to decode the encoded XOR3P instruction to generate a decoded XOR3P instruction; and execution circuitry to execute the decoded XOR3P instruction to: perform a rotate operation on the third value based on the fourth operand to generate a rotated third value; perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result; and perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR; and store the rotated XOR result. 1. A hardware processor, comprising: fetch circuitry to fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decode circuitry to decode the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and execution circuitry to execute the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value ; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result. 6. The hardware processor of claim 1, wherein the first rotational value and the second rotational value are based on a single bit in the fourth operand . 8. A method, comprising: fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction; and executing, by execution circuitry, to execute the decoded XOR3P instruction to: perform a rotate operation on the third value based on the fourth operand to generate a rotated third value; perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result; and perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR; and store the rotated XOR result. 8. A method, comprising: fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value ; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result. 13. The method of claim 8, wherein the first rotational value and the second rotational value are based on a single bit in the fourth operand . 15. A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to: fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decode the encoded XOR3P instruction to generate a decoded XOR3P instruction; and execute the decoded XOR3P instruction to: perform a rotate operation on the third value based on the fourth operand to generate a rotated third value; perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result; and perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR; and store the rotated XOR result. 15. A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to: fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decode the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and execute the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result. 20. The computer readable medium of claim 15, wherein the first rotational value and the second rotational value are based on a single bit in the fourth operand . 08-34 AIA Claim s 1 - 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 - 21 of U.S. Patent No. 12,197,921 . Although the claims at issue are not identical, they are not patentably distinct from each other because the differences between the claims are shown in the table below. First, labeling an instruction as an XOR3P instruction does not provide a patentable difference when both instructions accomplish the same processing. Secondly, both the Patent and the instant application include a limitation to “determine a first rotational value and a second rotational value.” It is seen that it would be obvious to one of ordinary skill to utilize said rotational value to “perform a first rotate operation using the first rotational value .” The dependent claims also have double patenting issues, but are omitted from the table below for brevity sake . 12,197,921 19/009066 1. A hardware processor, comprising: fetch circuitry to fetch an encoded instruction comprising at least one opcode, a first source identifier to identify a first register to store a first operand value , a second source identifier to identify a second register to store a second operand value , a third source identifier to identify a third register to store a third operand value , and a fourth operand value; decode circuitry to decode the encoded instruction to generate a decoded instruction; and execution circuitry to execute the decoded instruction to: determine a first rotational value and a second rotational value; perform a first rotate operation using the first rotational value , wherein the first rotate operation is to include a rotation of a 3 operand XOR result generated based on at least a portion of the first operand value, at least a portion of the second operand value, and at least a portion of the third operand value to generate a first rotated result; perform a second rotate operation on the first rotated result using the second rotational value to generate a second rotated result; and store the second rotated result. 1. A hardware processor, comprising: fetch circuitry to fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value; decode circuitry to decode the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and execution circuitry to execute the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result. 8. A method, comprising: fetching, by fetch circuitry, an encoded instruction comprising at least one opcode, a first source identifier to identify a first register to store a first operand value , a second source identifier to identify a second register to store a second operand value , a third source identifier to identify a third register to store a third operand value , and a fourth operand value; decoding, by decode circuitry, the encoded instruction to generate a decoded instruction; and executing, by execution circuitry, the decoded instruction to: determine a first rotational value and a second rotational value; perform a first rotate operation using the first rotational value , wherein the first rotate operation is to include a rotation of a 3 operand XOR result generated based on at least a portion of the first operand value, at least a portion of the second operand value, and at least a portion of the third operand value to generate a first rotated result; perform a second rotate operation on the first rotated result using the second rotational value to generate a second rotated result; and store the second rotated XOR result. 8. A method, comprising: fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to [identify] a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value ; decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result. 15. A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to: fetch an encoded instruction comprising at least one opcode, a first source identifier to identify a first register to store a first operand value , a second source identifier to identify a second register to store a second operand value , a third source identifier to identify a third register to store a third operand value , and a fourth operand value; decode the encoded instruction to generate a decoded instruction; and execute the decoded instruction to: determine a first rotational value and a second rotational value; perform a first rotate operation using the first rotational value , wherein the first rotate operation is to include a rotation of a 3 operand XOR result generated based on at least a portion of the first operand value, at least a portion of the second operand value, and at least a portion of the third operand value to generate a first rotated result; perform a second rotate operation on the first rotated result using the second rotational value to generate a second rotated result; and store the second rotated result. 15. A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to: fetch an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value ; decode the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and execute the decoded XOR3PP instruction to: determine a first rotational value and a second rotational value; perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value; perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result . 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 – 6, 8 – 13, and 15 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wolrich et al., U.S. Patent Application 2014/0189369 (hereinafter referred to as Wolrich) in view of Rawat et al., ‘SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje’ (hereinafter referred to as Rawat) . Referring to claim 1 , Wolrich discloses “A hardware processor, comprising: fetch circuitry to fetch” ( Fig. 3 and [0065] - [0067] processor with instruction fetch unit ) “an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register,” “wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value” ( Fig. 9 and [0113] “SHA256_2RND” instruction, "The instruction specifies or otherwise indicates a first source 914, specifies or otherwise indicates a second source 916, specifies or otherwise indicates a third source 944, and specifies or otherwise indicates a destination 918 ); “decode circuitry to decode the encoded XOR3PP instruction to generate a decoded XOR3PP instruction” ( Fig. 3 and [0065] - [0067] processor with decoder 313 ); “and execution circuitry to execute the decoded XOR3PP instruction” ( Fig. 3 and [0065] – [0067] execution logic 312 ) “to: determine a first rotational value and a second rotational value” ( [0075] processing of SHA2 round includes ai ROTR 2, ai ROTR 13, ai ROTR 22 ); “perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value” ( [0075] processing of SHA2 round includes ai ROTR 2, ai ROTR 13, ai ROTR 22 ); “perform an XOR operation on at least a portion of the first value, at least a portion of the second value” ( (a.sub.i ROTR 2) XOR (a.sub.i ROTR 13) XOR (a.sub.i ROTR 22) ); “and store the” “XOR result” ( Fig. 9 and [0113] destination register 918 ). Wolrich does not appear to explicitly disclose “a fourth source identifier to identify a fourth operand.” Also, Wolrich does not appear to explicitly disclose “perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.” However, Rawat discloses more SHA instructions ( Abstract and Introduction ) including an instruction including another “source identifier to identify” another “operand” ( section 4.2 immediate value as an operand, the immediate field contains the required rho offset value ). It would have been obvious to combine the teachings of Rawat’s operand for an immediate field containing rho offset values with the three operand instruction of Wolrich so that the immediate operand is a “fourth operand” and “a fourth source identifier to identify a fourth operand” is used in the instruction. Rawat also discloses an instruction to “perform an XOR operation on at least a portion of the first value” “and the rotated third value to generate an XOR result; perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result” ( section 2.2 describes Keccak steps theta includes rotate and XOR, rho includes rotate, X includes combining of bits of nearby lanes with AND, XOR, and NOT operations. Also see Fig. 4. section 4.1 with Figure 7 a) shows rotate a source data and XOR with another source data. section 4.2 with Figure 7 b) shows XOR two sources and rotate the result. These instructions accelerate calculations of Keccak by combining steps into a single instruction ). It would have been obvious to one of ordinary skill in the art to combine Rawat with Wolrich’s three operand instruction so that the instruction is to “perform an XOR operation on at least a portion of the first value, at least a portion of the second value , and the rotated third value to generate an XOR result.” Wolrich and Rawat are analogous art because they are from the same field of endeavor, which is SHA instructions. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Wolrich and Rawat before him or her, to modify the teachings of Wolrich to include the teachings of Rawat so that the instruction includes a fourth operand and the instruction performs an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result. The motivation for doing so would have been to provide an instruction that combines theta, rho, and pi steps of Keccak in a single instruction (as described by Rawat at section 4.2). Therefore, it would have been obvious to combine Rawat with Wolrich to obtain the invention as specified in the instant claim. As per claim 2 , Wolrich discloses “commit circuitry to commit a result of the executed transform instruction” ( Fig. 17A and [0182] commit stage 1724 ). As per claims 3 and 4 , Wolrich discloses “the first register is a 512-bit register that stores a 64-bit value” and “the first register stores eight 64-bit words” ( [0006 SHA-512 with message digest of 512-bits, eight state words each 64-bits, [0161] "The 512-bit registers ZMM0 through ZMM31 are operable to hold 512-bit packed data, 256-bit packed data, and/or 128-bit packed data" "Different data element sizes are supported including" "64-bit quadword" ). As per claim 5 , Wolrich discloses “the XOR3PP operation is performed on all eight words” ( [0009] eight state words are input to the round ). As per claim 6 , neither Wolrich nor Rawat appears to explicitly disclose “the first rotational value and the second rotational value are based on a single bit in the fourth operand.” However, as above, Rawat discloses “the first rotational value and the second rotational value” are based on bits “in the fourth operand” ( section 4.2 immediate value as an operand, the immediate field contains the required rho offset value ). It would have been obvious to one of ordinary skill in the art at the time of Applicant’s invention to utilize any number of bits to convey a rotational value. In other words, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s invention to modify Wolrich/Rawat so that “the first rotational value and the second rotational value are based on a single bit in the fourth operand.” A number of bits to represent a value is a design decision based on possible variants of the data, cost of extra bits, etc. Referring to claim 8, claim 1 recites the corresponding limitations as that of claim 8. Therefore, the rejection of claim 1 applies to claim 8. Note, claim 9 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 9. Note, claim 10 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 10. Note, claim 11 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 11. Note, claim 12 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 12. Note, claim 13 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 13. Referring to claim 15, claim 1 recites the corresponding limitations as that of claim 15. Therefore, the rejection of claim 1 applies to claim 15. Also, Wolrich discloses “A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to” carry out the steps of claim 1 (( [0163] – [0164] machine-readable storage medium ). Note, claim 16 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 16. Note, claim 17 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 17. Note, claim 18 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 18. Note, claim 19 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 19. Note, claim 20 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 20 . 07-21-aia AIA Claim s 7, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wolrich in view of Rawat, as applied to claims above, further in view of Wolrich et al., U.S. Patent Application 2014/0189368 (hereinafter referred to as Wolrich ‘368) . As per claim 7 , Wolrich discloses “the first source, the second source, and the third source are 512-bit long” and using “an 8-bit integer immediate” ( Fig. 9 and [0113] "The instruction specifies or otherwise indicates a first source 914, specifies or otherwise indicates a second source 916, specifies or otherwise indicates a third source 944, and specifies or otherwise indicates a destination 918. [0006] SHA-512 with message digest of 512-bits, eight state words each 64-bits, [0161] "The 512-bit registers ZMM0 through ZMM31 are operable to hold 512-bit packed data, 256-bit packed data, and/or 128-bit packed data" [0169] IMM8 1572 ). Neither Wolrich nor Rawat appears to explicitly disclose “the fourth source is an 8-bit integer immediate.” However, Wolrich ‘368 discloses another instruction for SHA hashing wherein another “source is an 8-bit integer immediate” ( [0043] rotate set specified by a field in an immediate operand. [0095] immediate byte ). It would have been obvious to combine the teachings of Wolrich ‘368 with the three operand instruction of Wolrich so that the immediate operand is a “fourth source.” Wolrich, Rawat, and Wolrich ‘368 are analogous art because they are from the same field of endeavor, which is SHA instructions. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Wolrich, Rawat, and Wolrich ‘368 before him or her, to modify the teachings of Wolrich and Rawat to include the teachings of Wolrich ‘368 so that the immediate operand is a “fourth source.” The motivation for doing so would have been to provide a flexible means for identifying input information (as described by Wolrich ‘368 at [0095]). Therefore, it would have been obvious to combine Wolrich ‘368 with Wolrich and Rawat to obtain the invention as specified in the instant claim. Note, claim 14 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 14. Note, claim 21 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 21 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Applications 20170147348, 20200117811 and Patents 9128698, 10725779, 11550582, 12026516 teach a single instruction with rotate and XOR. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN G SNYDER/Primary Examiner, Art Unit 2184 Application/Control Number: 19/009,066 Page 2 Art Unit: 2184 Application/Control Number: 19/009,066 Page 3 Art Unit: 2184 Application/Control Number: 19/009,066 Page 4 Art Unit: 2184 Application/Control Number: 19/009,066 Page 5 Art Unit: 2184 Application/Control Number: 19/009,066 Page 6 Art Unit: 2184 Application/Control Number: 19/009,066 Page 7 Art Unit: 2184 Application/Control Number: 19/009,066 Page 8 Art Unit: 2184 Application/Control Number: 19/009,066 Page 9 Art Unit: 2184 Application/Control Number: 19/009,066 Page 10 Art Unit: 2184 Application/Control Number: 19/009,066 Page 11 Art Unit: 2184 Application/Control Number: 19/009,066 Page 12 Art Unit: 2184 Application/Control Number: 19/009,066 Page 13 Art Unit: 2184 Application/Control Number: 19/009,066 Page 14 Art Unit: 2184 Application/Control Number: 19/009,066 Page 15 Art Unit: 2184 Application/Control Number: 19/009,066 Page 16 Art Unit: 2184 Application/Control Number: 19/009,066 Page 17 Art Unit: 2184 Application/Control Number: 19/009,066 Page 18 Art Unit: 2184 Application/Control Number: 19/009,066 Page 19 Art Unit: 2184 Application/Control Number: 19/009,066 Page 20 Art Unit: 2184 Application/Control Number: 19/009,066 Page 21 Art Unit: 2184 Application/Control Number: 19/009,066 Page 22 Art Unit: 2184 Application/Control Number: 19/009,066 Page 23 Art Unit: 2184 Application/Control Number: 19/009,066 Page 24 Art Unit: 2184 Application/Control Number: 19/009,066 Page 25 Art Unit: 2184 Application/Control Number: 19/009,066 Page 26 Art Unit: 2184 Application/Control Number: 19/009,066 Page 27 Art Unit: 2184 Application/Control Number: 19/009,066 Page 28 Art Unit: 2184 Application/Control Number: 19/009,066 Page 29 Art Unit: 2184 Application/Control Number: 19/009,066 Page 30 Art Unit: 2184 Application/Control Number: 19/009,066 Page 31 Art Unit: 2184 Application/Control Number: 19/009,066 Page 32 Art Unit: 2184 Application/Control Number: 19/009,066 Page 33 Art Unit: 2184 Application/Control Number: 19/009,066 Page 34 Art Unit: 2184 Application/Control Number: 19/009,066 Page 35 Art Unit: 2184 Application/Control Number: 19/009,066 Page 36 Art Unit: 2184
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