DETAILED ACTION
This Office action is in response to the application filed on 03 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 at line 8 recites, “a first rectification signal,” at line 10 recites again, “a first rectification signal,” at line 12 recites, “a third rectification signal,” then at line 17 recites, “the third signal” and “the second signal”.
Regarding the second instance of “a first rectification signal” it is not clear if this refers back to the already-introduced first rectification signal, or if it is intended to mean a second rectification signal.
Regarding the signals recited at line 17, there is a lack of antecedent basis for the third signal and for the second signal. It is not clear if these are different signals or if they should instead refer to the third rectification signal and the second rectification signal (assuming the instance at line 10 is meant to be a second rectification signal).
For purposes of examination, the recitation at line 10 of claim 4 is interpreted as a second rectification signal, and the recitations at line 17 are interpreted as the third rectification signal and the second rectification signal.
Claim 5 depends from claim 4 and is therefore indefinite due to inheriting the above deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 21-22 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wen et al. (US 2023/0369986; hereinafter “Wen”).
In re claims 1 and 21, Wen discloses a power conversion circuit and the corresponding control method thereof (see Fig. 3), comprising:
a resonant capacitor (Cr), coupled between a resonant node (between Cr, C1 and Lm) and a ground (ground, through unlabeled current sense resistor);
a transformer (TR), comprising a primary coil (Pw) and a secondary coil (Sw), wherein the primary coil is coupled between a switch node (node between Lm, Lk and S1) and the resonant node (node between Lm, Cr and C1);
a high-side transistor (SHS), providing an input voltage (Vin) to the switch node (through Lk/S1) based on a high-side driving signal (Hs);
a low-side transistor (SLS), coupling the switch node (through Lk/S1) to the ground (through unlabeled current sense resistor) based on a low- side driving signal (Ls);
a control circuit (20), generating the high-side driving signal (Hs) and the low-side driving signal (Ls) based on a feedback voltage (SHFBFB, SLLCFB), and operating in either a flyback mode (Abstract: hybrid flyback conversion mode or HFB mode) or a non-flyback mode (Abstract: resonance conversion mode or LLC mode) based on an output voltage (Abstract);
a feedback circuit (10), generating the feedback voltage (SHFBFB, SLLCFB) based on the output voltage (Vout; see [0009]); and
a rectification circuit (SR1, SR2, S3), full-wave (see [0029]: complementary switching conduction of both SR1, SR2) or half-wave (see [0030]: only SR1 is switched to provide a conduction path) rectifying energy of the secondary coil based on the output voltage to generate the output voltage (Abstract, [0037]);
wherein when the output voltage is lower than an output threshold, the control circuit operates in the flyback mode and the rectification circuit half-wave rectifies the energy of the secondary coil to generate the output voltage ([0037], [0030]: control circuit operates in HFB mode when Vout less than a window reference around a 28 V threshold and only SR1 operates to perform half-wave rectification).
In re claim 2, Wen discloses wherein the control circuit transitions from the flyback mode to the non-flyback mode, or from the non- flyback mode to the flyback mode, based on a signal edge of the low-side driving signal (Fig. 5: transition from HFB mode to LLC mode begins at last falling edge of Ls signal).
In re claims 3 and 22, Wen discloses wherein the secondary coil (Fig. 3: Sw) comprises a first secondary coil (W1) and a second secondary coil (W2), wherein when the output voltage is not less than the output threshold, the control circuit operates in the non-flyback mode and the rectification circuit full-wave rectifies the energy of the first secondary coil and the second secondary coil to generate the output voltage ([0029], [0037]: when Vout above a window reference around the 28V threshold, control circuit operates in LLC mode and both SR1 and SR2 are controlled to perform full-wave rectification).
In re claim 4, Wen discloses wherein the secondary coil Fig. 3: Sw) comprises a first secondary coil (W1) and a second secondary coil (W2),
wherein the first secondary coil comprises a first node (non-dotted end of W1) and a second node (Dotted end of W1), and the second secondary coil comprises a third node (non-dotted end of W2) and a fourth node (dotted end of W2),
wherein the first node and the fourth node are both coupled to the output voltage (Vout through S4);
wherein the rectification circuit comprises:
a first rectification transistor (SR1), coupling the second node (dotted end of W1) to the ground (ground) based on a first rectification signal (SSR1);
a second rectification transistor (SR2), coupling the third node (non-dotted end of W2) to a rectification node (node between S3, SR2) based on a [second] rectification signal (SSR2); and
a third rectification transistor (S3), coupling the rectification node to the ground based on a third rectification signal (SLLCOK);
wherein when the output voltage is lower than the output threshold, the third rectification transistor is turned off so that the rectification circuit half- wave rectifies the energy of the second secondary coil to generate the output voltage ([0030], [0037]: control circuit operates in HFB mode when Vout less than a window reference around a 28 V threshold and only SR1 operates to perform half-wave rectification);
wherein the third signal is synchronous with the second signal ([0029] i.e., they are both turned on at the same time when SSR2 is on during LLC mode; see Figs. 4-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wen in view of King (US 2019/0222131).
In re claims 6 and 23, Wen discloses the invention according to claims 1 and 21 as explained above, but does not further disclose wherein the transformer further comprises: an auxiliary coil, coupled between an auxiliary node and the ground; wherein the power conversion circuit further comprises a second divider dividing a voltage of the auxiliary node to generate a reflected voltage; wherein the reflected voltage is related to the output voltage; wherein the control circuit operates in either the flyback-mode or the non-flyback mode based on the reflected voltage.
Whereas King discloses the known and conventional use of an auxiliary transformer winding in an isolate DC-DC converter (Fig. 5: 506) together with a voltage divider (not shown; see [0070]) for sensing a reflected voltage in order to determine the output voltage therefrom ([0070]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter and method of Wen by incorporating an auxiliary coil, coupled between an auxiliary node and the ground; wherein the power conversion circuit further comprises a second divider dividing a voltage of the auxiliary node to generate a reflected voltage; wherein the reflected voltage is related to the output voltage; wherein the control circuit operates in either the flyback-mode or the non-flyback mode based on the reflected voltage as shown by King for the purpose of simplifying the detection and feedback of the output voltage.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-4 and 21-22 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 7-17 and 19-231 of copending Application No. 18/792,930 (reference application).
Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of the claims under provisional rejection in this application are found recited, either verbatim or nearly so, in the pending claims of the reference application. For example, all limitations found in instant claim 1 are found in claim 1 of the reference application except for the mode of operation being determined by the output voltage being lower/higher than an output threshold, which limitation is actually found recited in claims 8-9 of the reference application, which depend from independent claim 1. The same applies for the instant method claim 21, mutatis mutandis, corresponding to method claims 15-17 and 19-23 of the reference application.
Likewise, the instant dependent claims 3-4 and 22 are found recited in corresponding dependent claims of the reference application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 7-20 and 24-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, the closest prior art is Wen, disclosing the invention according to claim 4 as explained above. However, Wen does not further disclose wherein the rectification circuit further comprises: a secondary control circuit, comprising: a synchronous rectification controller, generating the first rectification signal based on a voltage of the second node and generating the second rectification signal based on a voltage of the third node; a first divider, dividing the output voltage to generate a first divided voltage; a first comparator, comparing the first divided voltage to a low voltage threshold to generate a rectification comparison signal; a first inverter, inverting the first rectification signal to generate a first inverted rectification signal; a first flip-flop, outputting the rectification comparison signal as a fourth rectification signal based on a signal edge of the first inverted rectification signal; and a second inverter, inverting the fourth rectification signal to generate the third rectification signal; wherein the second divided voltage is the output voltage multiplied by a first ratio, and the low voltage threshold is the output threshold multiplied by a second ratio; wherein the first ratio is equal to the second ratio.
Furthermore, the additional prior art on record does not suggest an obvious modification to the converter of Wen that would have resulted in these features of the claimed invention.
With respect to claim 7, the closest prior art is Wen as modified according to King, disclosing the invention according to claim 6 as explained above. However, Wen as modified does not further disclose wherein the control circuit further comprises: a mode determination circuit, comprising: a first pulse generator, generating a pulse signal based on the low-side driving signal; a determination AND gate, performing a logic AND operation on the low-side driving signal and the pulse signal to generate a sampling signal; a sampling switch, sampling the reflected voltage based on the sampling signal and storing the reflected voltage in a sampling capacitor as a sampling voltage; a first determination inverter, inverting the sampling signal to generate an inverted sampling signal; a second pulse generator, generating a hold signal based on the inverted sampling signal; a hold switch, sampling the sampling voltage based on the hold signal and storing the sampling voltage in a hold capacitor as a hold voltage; a determination comparator, comparing the hold voltage to a low voltage threshold to generate a determination signal; and a determination flip-flop, latching the determination signal as a mode signal based on an inverse of a high-side dead-time signal; wherein when the hold voltage is lower than the low voltage threshold, the determination signal and the mode signal are in a disabled state; wherein when the hold voltage is not less than the low voltage threshold, the determination signal and the mode signal are in an enabled state; wherein the low voltage threshold is the output threshold multiplied by a ratio.
Furthermore, the additional prior art on record does not suggest an obvious modification to the converter of Wen that would have resulted in these features of the claimed invention.
Claims 8-20 each depend, either directly or indirectly, from claim 7 and would therefore be allowable for the same reasons.
With respect to claim 24, the closest prior art is Wen as modified according to King, disclosing the invention according to claim 23 as explained above. However, Wen as modified does not further disclose wherein the step of determining whether the reflected voltage is lower than the low voltage threshold further comprises: sampling the reflected voltage to store as a sampling voltage based on the low- side transistor being turned on; sampling the reflected voltage to store as a hold voltage based on the low-side transistor being turned off; using a comparator to compare the hold voltage and the low voltage threshold to generate a determination signal, wherein when the hold voltage is not less than the low voltage threshold, the determination signal is in an enabled state, wherein when hold voltage is lower than the low voltage threshold, the determination signal is in a disabled state; latching the determination signal as a mode signal based on a high-side dead time of the high-side transistor; operating the power conversion circuit in the non-flyback mode when the mode signal is in the enabled state; and operating the power conversion circuit in the flyback mode when the mode signal is in the disabled state.
Furthermore, the additional prior art on record does not suggest an obvious modification to the converter of Wen that would have resulted in these features of the claimed invention.
With respect to claim 25, the closest prior art is Wen as modified according to King, disclosing the invention according to claim 23 as explained above. However, Wen as modified does not further disclose using a first current detection circuit to detect a current flowing through the resonant capacitor to generate a current detection signal; integrating the current detection signal based on a reference voltage to generate an integrated signal; full-wave rectifying the integrated signal to generate a rectified signal; and driving the high-side transistor and the low-side transistor based on the rectified signal; wherein the first current detection circuit comprises a first capacitor and a first resistor; wherein the first capacitor is coupled between the resonant node and a first detection node, and the first resistor is coupled between the first detection node and the ground; wherein the current detection signal is generated at the first detection node; wherein a second capacitor is coupled between the first detection node and a second detection node.
Furthermore, the additional prior art on record does not suggest an obvious modification to the converter of Wen that would have resulted in these features of the claimed invention.
Claims 26-31 each depend, either directly or indirectly, from claim 5 and would therefore be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2007/0221267 discloses a Method And Apparatus For Converting Direct Current To Alternating Current operable in a flyback mode and a quasi-resonant mode.
US Patent 11,658,581 discloses a Power Converter With Adjustable Output Voltage which switches between flyback mode and LLC mode of operation based on output voltage, and which further operates to either half-wave or full-wave rectify the secondary voltage based on the mode of operation.
US 2023/0353057 discloses a CHARGER which is operable to switch between a resonance mode and a flyback mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 This provisional rejection is based on the amended claim set filed on 29 June 2026 in the reference application.
Prosecution Insights