DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 04/27/2026. Claims 1-20 have been examined and are pending in this application.
Response to Arguments
Applicant's arguments filed 04/27/2026 have been fully considered but they are not persuasive.
Applicant argues, page 12 of the remarks, “Turning to the rejection of record, Colella does not teach or suggest the merging of segment bitmaps that correspond to two different storage blocks. Instead, Colella discloses combining an existing virtual block VB bitmap and an updated virtual block VB bitmap to identify and update a logical to physical address translation L2P bitmap. Colella expressly states that a VB map is created for each L2P table in paragraphs [0020], [0021], and discloses that the combined VB bitmaps are pre-update and post-update bitmaps corresponding to the same storage block in paragraphs [0064] through [0068].”
The Examiner respectfully disagrees. The Examiner respectfully submits that Applicant is misinterpreting a “virtual block” taught by Colella. That is the reason behind all the confusion by the Applicant.
Colella teaches “A virtual block (VB) can be formed by the union of physical blocks belonging to each plane on different NAND dice located in a particular packaged memory device. For example, if there are four dice, and each die has four planes, the VB can be the union of slices (e.g., physical blocks) across the planes of each of the dice. Thus, in this example, each VB would be the union of 16 physical blocks.” Paragraph [0017] and FIG. 1C of Colella. See FIG. 1C of Colella for examples of virtual blocks that depend on the organization of the memory device. That is, a virtual block (VB) represents a collection of physical storage blocks dependent on the organization of the memory device. A virtual block (VB) bitmap of Colella is the same as “a segment bitmap 300 so that two or more storage blocks 111 correspond to each segment bitmap 300,” of the instant disclosed invention. See paragraph [00120] of the instant filed specification.
Further, Colella teaches “The controller can create a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points. The controller can create an updated VB bitmap for a particular L2P table based on changes to the particular L2P table due to programming the virtual blocks after closing the particular L2P table.” Paragraph [0021] of Colella. A VB bitmap is a bitmap corresponding to a plurality of physical storage blocks. Therefore, a VB bitmap and the updated VB bitmap correspond to mapping information for a plurality of physical storage blocks including a first physical storage block and a second physical storage block that is different from the first physical storage block.
Applicant argues, page 13 of the remarks, “In addition, Colella does not teach or suggest dynamical changes to the total size of segment bitmaps loaded into the buffer memory depending on the data movement operation. Since the controller loads two or more segment bitmaps for a first data movement operation and loads one segment bitmap for a second data movement operation, the total size of loaded segment bitmaps dynamically changes. In contrast, Colella discloses that the combined size of the existing VB bitmap and the updated VB bitmap is always a fixed value (two bitmaps) to perform an XOR operation.”
The Examiner respectfully disagrees. Further, the Examiner respectfully submits that Colella nowhere discloses “the combined size of the existing VB bitmap and the updated VB bitmap is always a fixed value (two bitmaps) to perform an XOR operation” as argued by the Applicant.
Colella teaches “the processing logic generates an updated VB bitmap for each updated L2P table that was flushed.” Paragraph [0070]. Colella further teaches “the processing logic performs an exclusive OR operation [e.g., a merge operation] between the VB bitmap and the updated VB bitmap for each respective L2P table that was flushed to determine one or more entries, corresponding to respective virtual blocks, in the VB bitmap that have flipped values within the updated VB bitmap.” Paragraph [0071]. Also see FIG. 3. An updated L2P table is flushed, paragraph [0084] of Colella. Since a VB bitmap and the corresponding updated VB bitmap are associated with a L2P table, see paragraph [0021] of Colella, the number of VB bitmap/Updated VB bitmap that are considered during the merge operation depends on the number of updated L2P tables. As a result, the combined sizes of the VB bitmap/updated VB bitmap may also be different for each merge operation.
In view of the foregoing remarks, independent claims 1, 13, and 17 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Colella et al. US 2024/0168889 (“Colella”).
As per independent claim 1, Colella teaches A storage device (“FIG. 1B illustrates the example memory sub-system 110 of FIG. 1A in which the memory device 130 includes multiple memory dice 134 and multiple channels 124,” para 0041) comprising:
a memory (“memory device 130” para 0041 and FIGS. 1A-B), including a plurality of storage blocks (“The memory cells of the memory devices 130 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.” Para 0033), each of the plurality of segment bitmaps (“The controller can create a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points.” Para 0021) including bit information indicating a mapping slice (“The controller can create an L2P bitmap for a respective virtual block, the L2P bitmap identifying logical addresses, within each respective L2P table, that belong to the respective virtual block.” Para 0021) that corresponds to at least one of the plurality of storage blocks, the mapping slice including mapping data associated with the corresponding storage block (“The controller can create an L2P bitmap for a respective virtual block, the L2P bitmap identifying logical addresses, within each respective L2P table, that belong to the respective virtual block.” Para 0021);
a controller (“memory sub-system controller 115” para 0041 and FIGS. 1A-B) configured to, generate a merged segment bitmap by loading a first segment bitmap and a second segment bitmap from among the plurality of segment bitmaps into a buffer memory and merging the first segment bitmap and the second segment bitmap (“the method 300B is performed by the dynamic bitmap tracker 113 of FIGS. 1A-1B.” Para 0068. “At operation 360, the VB bitmap and the updated VB bitmap are combined.” Para 0071 and FIG. 3B. “The controller 115 (e.g., the dynamic bitmap tracker 113) can store L2P bitmaps 150 and VB bitmaps 160 to the local memory 119.” Para 0041. Therefore, the VB bitmap and the updated VB bitmap are loaded into a volatile memory 119),
load at least one mapping slice indicated by the merged segment bitmap into the buffer memory (“At operation 365, each impacted L2P bitmap is loaded into the volatile memory.” Para 0072 and FIG. 3B),
search for a valid page for a first data movement operation using the at least one mapping slice (“the method 400 is performed by the dynamic bitmap tracker 113 and/or the controller 115 of FIGS. 1A-1B.” Para 0080 and FIG. 4. “At operation 420, valid logical addresses are identified.” Para 0082 and FIG. 4. “At operation 430, data is migrated to a new virtual block.” Para 0083 and FIG. 4);
wherein the first segment bitmap indicates a mapping slice including mapping data associated with a first storage block, and the second segment bitmap indicates a mapping slice including mapping data associated with a second storage block different from the first storage block (“The controller can create a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points. The controller can create an updated VB bitmap for a particular L2P table based on changes to the particular L2P table due to programming the virtual blocks after closing the particular L2P table.” Paragraph [0021] of Colella. A VB bitmap is a bitmap corresponding to a plurality of physical storage blocks (see paragraph [0017]). Therefore, a VB bitmap and the updated VB bitmap correspond to mapping information for a plurality of physical storage blocks including a first physical storage block and a second physical storage block that is different from the first physical storage block).
In FIG. 1B, Colella teaches that “the local memory 119 is fast-access volatile memory such as SRAM or TCM.” Para 0041. Further, “The controller 115 … can store L2P bitmaps 150 and VB [Virtual Block] bitmaps 160 to the local memory 119.” Para 0041. The claimed invention (see dependent claim 12), however, stores the segment bitmaps in a non-volatile memory. Therefore, Colella does not explicitly teach “that stores a plurality of segment bitmaps”.
However, FIG. 3A of Colella is a flow diagram of an example method 300A for creating a virtual block (VB) bitmap for an L2P table. At operation 320, the L2P table is read from the dice of the memory device 130. Para 0064. At operation 330, a VB bitmap is created. Para 0066. A VB bitmap is mapped to the claimed segment bitmap.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Colella with “that stores a plurality of segment bitmaps”. The motivation would be that the VB bitmap can be quickly accessed from the fast-access volatile memory such as SRAM or TCM, para 0041 of Colella.
As per dependent claim 2, Colella discloses the device of claim 1. Colella teaches wherein the plurality of storage blocks includes two or more object storage blocks and a target storage block, and the controller copies a valid page stored in the two or more object storage blocks from among the plurality of storage blocks to the target storage block in the first data movement operation (“At operation 420, valid logical addresses are identified. More specifically, the processing logic identifies, based on at least one L2P table associated with the identified virtual block, valid logical addresses associated with valid data stored in the identified virtual block. At operation 430, data is migrated to a new virtual block.” Paras 0082-0083 and FIG. 4).
As per dependent claim 3, Colella discloses the device of claim 1. Colella teaches wherein the plurality of storage blocks includes two or more object storage blocks and a target storage block, and wherein, in the first data movement operation, the controller copies a valid page stored in an object storage block storing data in a first memory cell type to the target storage block storing data in a second memory cell type (“At operation 430, data is migrated to a new virtual block.” Paras 0082-0083 and FIG. 4. Colella does not explicitly teach that data is migrated from a block of a first memory cell type to a block storing data in a second memory cell type. However, Colella teaches “a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells.” Para 0032. Therefore, Colella inherently teaches migrating data from a block having a first memory cell type to a block having a second memory cell type).
As per dependent claim 4, Colella discloses the device of claim 1. Colella teaches wherein a number of free storage blocks included in the plurality of storage blocks increases after the first data movement operation (“At a certain point, there is no more availability of empty [mapped to free] VBs and the controller can perform media management (also called a garbage collection (GC) operation) by which to move valid data from a source VB to a destination VB to free up the source VB.” Para 0018).
As per dependent claim 5, Colella discloses the device of claim 1. Colella teaches wherein the controller loads one segment bitmap from among the plurality of segment bitmaps into the buffer memory, loads at least one mapping slice indicated by the one segment bitmap into the buffer memory, and searches for a valid page for a second data movement operation using the at least one mapping slice (“At operation 365, each impacted L2P bitmap is loaded into the volatile memory. … At operation 385, additional L2P bitmaps are loaded. More specifically, if additional L2P bitmaps were impacted by a bit-flip, at operation 365 the processing logic iteratively loads another L2P bitmap into volatile memory to be updated.” Paras 0072-0074 and FIG. 3B. “At operation 420, valid logical addresses are identified.” Para 0082 and FIG. 4).
As per dependent claim 6, Colella discloses the device of claim 5. Colella teaches wherein the plurality of storage blocks includes two or more object storage blocks and a target storage block, and wherein the controller copies a valid page stored in one object storage block to the target storage block according to the second data movement operation (“At operation 420, valid logical addresses are identified. More specifically, the processing logic identifies, based on at least one L2P table associated with the identified virtual block, valid logical addresses associated with valid data stored in the identified virtual block. At operation 430, data is migrated to a new virtual block.” Paras 0082-0083 and FIG. 4).
As per dependent claim 7, Colella discloses the device of claim 5. Colella teaches wherein the controller copies a valid page stored in an object storage block to a target storage block according to the first data movement operation or the second data movement operation, wherein a number of bits stored in a memory cell included in the target storage block is greater than or equal to a number of bits stored in a memory cell included in the object storage block (“a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells.” Para 0032. Since the memory device includes multiple portions of multiple cell types each type having a different number of bits, after the migration operation (operation 430, FIG. 4), the number of bits of the cell where data is migrated to would be different than a number of bits of the cell of the source block from which data is migrated).
As per dependent claim 8, Colella discloses the device of claim 5. Colella teaches wherein a total size of the segment bitmaps loaded into the buffer memory before loading the at least one mapping slice into the buffer memory for the first data movement operation is larger than a total size of the segment bitmap loaded into the buffer memory before loading the at least one mapping slice into the buffer memory for the second data movement operation (“the processing logic generates an updated VB bitmap for each updated L2P table that was flushed.” Paragraph [0070]. Colella further teaches “the processing logic performs an exclusive OR operation [e.g., a merge operation] between the VB bitmap and the updated VB bitmap for each respective L2P table that was flushed to determine one or more entries, corresponding to respective virtual blocks, in the VB bitmap that have flipped values within the updated VB bitmap.” Paragraph [0071]. Also see FIG. 3. An updated L2P table is flushed, paragraph [0084] of Colella. Since a VB bitmap and the corresponding updated VB bitmap are associated with a L2P table, see paragraph [0021] of Colella, the number of VB bitmap/Updated VB bitmap that are considered during the merge operation depends on the number of updated L2P tables. As a result, the combined sizes of the VB bitmap/updated VB bitmap may also be different for each merge operation).
As per dependent claim 9, Colella discloses the device of claim 1. Colella teaches wherein the controller sets bit information of the merged segment bitmap corresponding to bit information having a valid value, in at least one of the first segment bitmap or the second segment bitmap, to a valid value and generates the merged segment bitmap (“if the entry has been reset in the VB bitmap (1->0), processing logic resets a bit in an entry of the identified L2P bitmap corresponding to the virtual block. Further, if the entry has been set in the VB bitmap (0->1), the processing logic sets a bit in an entry of the identified L2P bitmap corresponding to the virtual block.” Para 0058 and FIG. 2).
As per dependent claim 10, Colella discloses the device of claim 1. Colella teaches wherein the controller generates the merged segment bitmap if at least one of a number of valid pages included in the storage block corresponding to the first segment bitmap or a number of valid pages included in the storage block corresponding to the second segment bitmap is less than or equal to a preset reference value (“At operation 410, a virtual block (VB) is identified. More specifically, the processing logic identifies, using the L2P bitmaps, which include the identified L2P bitmap from operation 290 (FIG. 2), a virtual block of the virtual blocks having a minimum amount of valid data.” Para 0081 and FIG. 4).
As per dependent claim 11, Colella discloses the device of claim 1. Colella teaches wherein at least one of the mapping data included in the at least one mapping slice indicates a virtual page number included in a storage block other than a storage block corresponding to the first segment bitmap and a storage block corresponding to the second segment bitmap (“This mask of bits may identify which entries in L2P tables point to the virtual pages (identified by logical address) that belong to a current VB to which the controller 115 is writing.” Para 0045).
As per dependent claim 12, Colella discloses the device of claim 1. Colella teaches wherein the plurality of segment bitmaps are stored in a storage block, from among the plurality of storage blocks, that stores data in a single-level cell type (“a particular memory device can include an SLC portion” para 0032).
As per independent claim 13, this claim is rejected based on arguments provided above for similar rejected independent claim 1 and dependent claim 8.
As per dependent claim 14, this claim is rejected based on arguments provided above for similar rejected dependent claims 2 and 5.
As per dependent claims 15-16, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 3-4.
As per independent claim 17, this claim is rejected based on arguments provided above for similar rejected independent claim 1 and dependent claim 8.
As per dependent claims 18-20, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 1, 10, and 12.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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