DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gillespie et al. (US 5543590, hereafter Gillespie).
Regarding claim 1, Gillespie teaches a programmable drive-sense unit (DSU) comprising:
a drive-sense circuit operably coupled to a load (Fig. 3, Col. 11 lines 27-47, where the charge integrator circuits 44-1 through 44-n are coupled to capacitors 42-1 through 42-n), wherein the drive-sense circuit is configured to:
drive and simultaneously to sense the load via a single line (Fig. 3, Col. 11 lines 27-59, where the circuits 44 bias or drive the capacitor and also capture the resulting voltage); and
produce an analog output based on the sensing the load in accordance with a first set of programmable operational parameters (Fig. 3, Col. 12 lines 13-38, where an analog output voltage is produced according to set timing parameters that control the capturing or sampling of a snapshot of the voltage); and
an analog to digital circuit (Fig. 3, Col. 12 lines 38-47, where there is an A/D converter 52) configured to:
generate a digital output based on the analog output and in accordance with a second set of programmable operational parameters (Fig. 3, Col. 12 line 38 to Col. 13 line 21, where the A/D converter outputs a digital output according to the input voltage parameters).
Regarding claim 2, Gillespie teaches the programmable DSU of claim 1 further comprises: a digital filtering circuit configured to: generate filtered data based on the digital output and in accordance with a third set of programmable operational parameters (Fig. 3, Col. 12 lines 13-38, where an analog output voltage is sampled and held according to set timing parameters by filter circuits 48 that capture or sample a snapshot of the voltage).
Regarding claim 3, Gillespie teaches the programmable DSU of claim 2 further comprises: a data processing circuit configured to: generate output data based on the filtered data in accordance with a fourth set of programmable operational parameters (Fig. 3, Col. 12 lines 29-47, where sample/hold circuits 50 process the data and are configured accordingly).
Regarding claim 4, Gillespie teaches the programmable DSU of claim 3 wherein a programmable operational parameter of the programmable operational parameters comprises a frequency for a rate of the output data (Col. 20, lines 30-50; Col. 7, lines 25-39, where the acquisition rate can be set).
Regarding claim 5, Gillespie teaches the programmable DSU of claim 1, wherein a programmable operational parameter of the programmable operational parameters comprises a number of reference signals (Col. 12 line 55 to Col. 13 line 13, where there are reference minimum and maximum signals).
Regarding claim 6, Gillespie teaches the programmable DSU of claim 5, wherein a programmable operational parameter of the programmable operational parameters comprises a waveform for at least one of the reference signals (Col. 12 line 55 to Col. 13 line 13, where the reference signals are dynamic such that they have the waveform of any common mode noise present in the system).
Regarding claim 7, Gillespie teaches the programmable DSU of claim 5, wherein another programmable operational parameter of the programmable operational parameters comprises a frequency for at least one of the reference signals (Col. 12 line 55 to Col. 13 line 13, where the reference signals are dynamic such that they have the frequency of any common mode noise present in the system).
Regarding claim 8, Gillespie teaches the programmable DSU of claim 5, wherein another programmable operational parameter of the programmable operational parameters comprises a phase for at least one of the reference signals (Col. 12 line 55 to Col. 13 line 13, where the reference signals are dynamic such that they have the phase of any common mode noise present in the system).
Regarding claim 9, Gillespie teaches the programmable DSU of claim 1, wherein a programmable operational parameter of the programmable operational parameters comprises a scaling factor (Col. 4, lines 55-66; Col. 12 line 48 to Col. 13 line 13, where the output digital voltage is scaled appropriately).
Regarding claim 10, Gillespie teaches the programmable DSU of claim 1, wherein a programmable operational parameter of the programmable operational parameters comprises a number of filtering stages to activate (Fig. 3, Col. 12 lines 13-38, where an analog output voltage is sampled and held according to set timing parameters by filter circuits 48 that capture or sample a snapshot of the voltage).
Regarding claim 11, Gillespie teaches the programmable DSU of claim 10, wherein another programmable operational parameter of the programmable operational parameters comprises a number of filter coefficients (Fig. 3, Col. 12 lines 13-38, where the filter circuits include coefficients for removing high frequency noise).
Regarding claim 12, Gillespie teaches the programmable DSU of claim 1, wherein a programmable operational parameter of the programmable operational parameters comprises a gain (Col. 12, lines 29-67, where the input analog signal is fit to an output digital signal, necessarily having a gain according to the minimum and maximum voltage of the output signal compared to the input signal).
Regarding claim 16, Gillespie teaches the programmable DSU of claim 1, wherein a first programmable operational parameter of one or more of the first, and second sets of programmable operational parameters is the same for each set of first and second sets of programmable operational parameters that includes the first programmable operational parameter (Fig. 3, Col. 12 line 19 to Col. 13 line 29, where control circuitry 56 controls operation of the filtering circuits and processing circuits according to a same operational process).
Regarding claim 17, Gillespie teaches the programmable DSU of claim 1, wherein one or more of the first and second sets of programmable operational parameters are based on achieving one or more load sensing objectives associated with the sensing of the load (Fig. 3, Col. 12 line 19 to Col. 13 line 29, where control circuitry 56 controls the drive/sense operation to achieve noise reduction and improved sensitivity).
Regarding claim 18, Gillespie teaches the programmable DSU of claim 17, wherein the load sensing objectives comprise one or more of: a signal to noise ratio; a sensitivity; a bandwidth; a sampling rate; and a power (Fig. 3, Col. 12 line 19 to Col. 13 line 29, where control circuitry 56 controls the drive/sense operation to achieve noise reduction and improved sensitivity).
Regarding claim 19, Gillespie teaches the programmable DSU of claim 1, wherein the drive-sense circuit further comprises: a comparator configured to produce the analog output based on comparison of a reference signal to a drive-sense signal, wherein the reference signal is received at a first input of the comparator, and the drive-sense signal is received at a second input of the comparator, and wherein the second input is coupled to the single line (Fig. 10, Col. 24, lines 9-34, where there is an amplifier 212 having compared inverting and non-inverting inputs, one being connected to a fixed reference signal and the other to the output of the filter circuit).
Regarding claim 20, Gillespie teaches the programmable DSU of claim 19, wherein the drive-sense circuit further comprises: a feedback circuit operably coupled to the comparator and configured to process the analog output to generate a control signal; and a dependent current supply operably coupled to the feedback circuit and configured to generate the drive-sense signal based on the control signal and to provide the drive-sense signal via the single line (Fig. 4b, Col. 14 line 50 to Col. 15 line 26, where the integrator 44 includes a feedback circuit coupled to the comparator and functions to generate the drive-sense signal to the OUT terminal; Fig. 10, Col. 24 lines 9-23, where there is a circuit acting as a current source running a feedback loop, VBIAS acting as a control signal for the charge integrator 44).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Gillespie et al. (US 5543590, hereafter Gillespie) in view of Tasher et al. (US 20090046827 A1, hereafter Tasher).
Regarding claim 13, Gillespie would show the programmable DSU of claim 1. But, Gillespie does not explicitly teach the programmable DSU wherein a programmable operational parameter of the programmable operational parameters comprises a number of clock signals. However, this was well known in the art as evidenced by Tasher (Figs. 5 and 6, [0091], where there is a clock generator outputting clock signals to control operation of the drive/sense device). Both Gillespie and Tasher teach drive/sense units. Gillespie is silent with respect to the use of a clock signal, although does teach that the acquisition rate of the device is configurable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tasher in the device of Gillespie to implement rate control using a clock signal and that such an implementation would have yielded a predictable result.
Regarding claim 14, the combination of Gillespie and Tasher would show the programmable DSU of claim 13. Tasher in the combination further teaches the programmable DSU wherein another programmable operational parameter of the programmable operational parameters comprises a waveform for at least one of the clock signals (Fig. 6, where the clock signal has a square waveform).
Regarding claim 15, the combination of Gillespie and Tasher would show the programmable DSU of claim 13. Tasher in the combination further teaches the programmable DSU wherein another programmable operational parameter of the programmable operational parameters comprises a frequency for at least one of the clock signals ([0091], where the frequency of the clock signal is configurable).
Conclusion
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/PETER D MCLOONE/Primary Examiner, Art Unit 2621