DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/10/2025 and 05/04/2026 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizuka U.S. Patent Application 2006/0087781 (hereinafter “Ishizuka”).
Regarding claim 1, Ishizuka teaches an integrated circuit (i.e. semiconductor integrated circuit 2)(fig.1) comprising: a buffer circuit (i.e. input/output buffer 31)(fig.1) coupled between a first node (i.e. VCC 5)(fig.1) and a second node (i.e. VSS 6)(fig.1); an input/output (IO) pad (i.e. I/O pad 33)(fig.1) coupled to the buffer circuit (implicit)(refer to fig.1), the buffer circuit being configured to output a first signal to the IO pad (implicit)(refer to fig.1); a first clamp circuit (i.e. diode 37)(fig.1) coupled between the IO pad and the second node (implicit)(refer to fig.1), and being configured to clamp a first electrostatic discharge (ESD) event at the IO pad or the second node (refer to [0045]); and a second clamp circuit (i.e. diode 36)(fig.1) coupled between the IO pad and the first node (implicit)(refer to fig.1), and being configured to clamp a second ESD event at the IO pad or the first node (refer to [0045]).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sugiura U.S. Patent Application 2010/0001347 (hereinafter “Sugiura”).
Regarding claim 20, Sugiura teaches a method of operating an electrostatic discharge (ESD) circuit (refer to [0052]-[0054] and figure 6), the method comprising: receiving a first ESD voltage (i.e. ESD)(fig.6)(refer also to [0052]) on a first node (i.e. input/output terminal)(fig.6), the first ESD voltage being greater than a reference supply voltage of a reference voltage supply (refer to [0052]), the first ESD voltage corresponding to a first ESD event (implicit)(refer to [0052]); detecting, by a first ESD detection circuit (i.e. trigger circuit)(figs.1 and 6), the first ESD event at the first node thereby causing the first ESD detection circuit to turn on (refer to [0052] and [0053]) and charge a first gate of a first transistor (i.e. MOSFET 2)(fig.6) of a first discharging circuit (refer to [0052] and [0053]), the first transistor being coupled between the first node and a second node (i.e. ground terminal)(fig.6), and the first ESD detection circuit being coupled between at least the first node and the second node (implicit)(refer to fig.6); and discharging a first ESD current of the first ESD event in a first ESD direction from the first node to the second node by the first transistor (refer to [0054]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizuka as applied to claim 1 above, and further in view of Sugiura.
Regarding claim 2, Ishizuka teaches the integrated circuit of claim 1; however, Ishizuka does not teach wherein the first clamp circuit comprises: a first ESD detection circuit coupled between the IO pad and the second node; and a first transistor of a first type, the first transistor including a first gate coupled to at least the first ESD detection circuit by a third node, a first drain coupled to the IO pad and a first source coupled to the second node. However, Sugiura teaches wherein the first clamp circuit comprises: a first ESD detection circuit (i.e. first trigger circuit)(fig.12) coupled between the IO pad (i.e. input/output terminal)(fig.12) and the second node (i.e. ground terminal)(fig.12); and a first transistor (i.e. NMOSFET 13)(fig.12) of a first type (implicit), the first transistor including a first gate (i.e. gate electrode 16)(fig.12) coupled to at least the first ESD detection circuit by a third node (implicit), a first drain coupled to the IO pad and a first source coupled to the second node (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Ishizuka to include the clamp circuits of Sugiura to provide the advantage of adjusting the trigger voltage of the clamps to fit the circuit and allowing a greater amount of current through the clamp during an ESD event.
Regarding claim 3, Ishizuka and Sugiura teach the integrated circuit of claim 2, wherein the first ESD detection circuit comprises: a first set of diodes (i.e. diodes 14)(fig.12) serially coupled to each other (implicit), and coupled between the IO pad and the third node (implicit); and a first resistor (i.e. resistance 15)(fig.12) coupled between the third node and the second node (implicit).
Regarding claim 4, Ishizuka and Sugiura teach the integrated circuit of claim 3, wherein the first set of diodes comprises: a first diode (i.e. Sugiura first diode in the figure below)(fig.12) including a first anode (implicit) and a first cathode (implicit), the first anode being coupled to the IO pad (implicit); a second diode (i.e. Sugiura second diode in the figure below)(fig.12) including a second anode (implicit) and a second cathode (implicit), the second anode being coupled to the first cathode (implicit); and a third diode (i.e. Sugiura third diode in the figure below)(fig.12) including a third anode (implicit) and a third cathode (implicit), the third anode being coupled to the second cathode (implicit).
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Regarding claim 5, Ishizuka and Sugiura teach the integrated circuit of claim 4, wherein the third cathode is coupled to the third node, the first gate and a first end of the first resistor (implicit)(refer to Sugiura fig.12).
Claim(s) 6-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizuka and Sugiura as applied to claim 4 above, and further in view of Ma et al. U.S. Patent No. 7,859,803 (hereinafter “Ma”).
Regarding claim 6, Ishizuka and Sugiura teach the integrated circuit of claim 4; however, they do not teach wherein the first clamp circuit further comprises: a fourth diode including a fourth anode and a fourth cathode, the fourth anode being coupled to the IO pad, and the fourth cathode being coupled to the first drain. However, Ma teaches wherein the first clamp circuit further comprises: a fourth diode (i.e. diode D5)(fig.8) including a fourth anode (implicit) and a fourth cathode (implicit), the fourth anode being coupled to the IO pad (implicit)(refer to PAD)(fig.8), and the fourth cathode being coupled to the first drain (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify clamps of the integrated circuit of Ishizuka and Sugiura to include the diode between the I/O pad and the transistor of Ma to provide the advantage of adjusting the clamp voltage to suit the circuit and lowering the voltage across the transistor, thereby preventing damage to the transistor.
Regarding claim 7, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 6, wherein the first set of diodes further comprises: a fifth diode (implicit)(refer to Sugiura diode 14)(fig.12)(refer to Ma diode string D2)(fig.8) including a fifth anode (implicit) and a fifth cathode (implicit), the fifth anode being coupled to the third cathode (implicit), and the fifth cathode being coupled to the third node, the first gate and a first end of the first resistor (implicit).
Regarding claim 8, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 7, wherein the second clamp circuit comprises: a second ESD detection circuit (i.e. Sugiura second trigger circuit)(fig.12) coupled between the IO pad and the first node (i.e. Sugiura power supply)(fig.12); and a second transistor (i.e. Sugiura PMOSFET 18)(fig.12) of a second type different from the first type (implicit), the second transistor including a second gate (i.e. Sugiura gate electrode 21)(fig.12) coupled to at least the second ESD detection circuit by a fourth node (implicit), a second drain coupled to the IO pad and a second source coupled to the second node (implicit).
Regarding claim 9, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 8, wherein the second ESD detection circuit comprises: a second set of diodes (i.e. Sugiura diodes 19)(fig.12) serially coupled to each other (implicit) and coupled between the IO pad and the fourth node (implicit); and a second resistor (i.e. Sugiura resistance 20)(fig.12) coupled between the fourth node and the first node (implicit).
Regarding claim 10, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 9, wherein the second set of diodes comprises: a sixth diode (i.e. Sugiura sixth diode in the figure above)(fig.12) including a sixth anode (implicit) and a sixth cathode (implicit), the sixth anode being coupled to the fourth node, the second gate and a first end of the second resistor (implicit); a seventh diode (i.e. Sugiura seventh diode in the figure above)(fig.12) including a seventh anode (implicit) and a seventh cathode (implicit), the seventh anode being coupled to the sixth cathode (implicit); and an eighth diode (i.e. Sugiura eighth diode in the figure above)(fig.12) including an eighth anode (implicit) and an eighth cathode (implicit), the eighth anode being coupled to the seventh cathode (implicit).
Regarding claim 11, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 10; however, they do not teach wherein the second clamp circuit further comprises: a ninth diode including a ninth anode and a ninth cathode, the ninth anode being coupled to the second drain, and the ninth cathode being coupled to the IO pad. However, Ma teaches a diode between a transistor and a pad (refer to fig.8)(refer also to the rejection of claim 6 above). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Ishizuka, Sugiura, and Ma to include a diode between the drain and pad of both the first and second clamp circuits of Ishizuka, Sugiura, and Ma to provide the advantage of adjusting the clamp voltage to suit the circuit and lowering the voltage across the transistor, thereby preventing damage to the transistor.
Regarding claim 12, Ishizuka, Sugiura, and Ma teach the integrated circuit of claim 11, wherein the second set of diodes further comprises: a tenth diode(implicit)(refer to Sugiura diode 19)(fig.12)(refer to Ma diode string D2)(fig.8) including a tenth anode (implicit) and a tenth cathode (implicit), the tenth anode being coupled to the eighth cathode (implicit), and the tenth cathode being coupled to the IO pad and the ninth cathode (implicit).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizuka and further in view of Wertheimer et al. U.S. Patent Application 2008/0074813 (hereinafter “Wertheimer”).
Regarding claim 13, Ishizuka teaches an integrated circuit (i.e. semiconductor integrated circuit 2)(fig.1) comprising: a buffer circuit (i.e. input/output buffer 31)(fig.1) including an input and an output (implicit), and being coupled between a first node (i.e. VCC 5)(fig.1) and a second node (i.e. VSS 6)(fig.1); an input/output (IO) pad (i.e. I/O pad 33)(fig.1) coupled to the output of the buffer circuit (implicit)(refer to fig.1), the IO pad being configured to receive a first signal from the buffer circuit (implicit)(refer to fig.1); a first clamp circuit (i.e. diode 37)(fig.1) coupled between the IO pad and the second node (implicit)(refer to fig.1), and being configured to clamp a first electrostatic discharge (ESD) event at the IO pad or the second node (refer to [0045]); a second clamp circuit (i.e. diode 36)(fig.1) coupled between the IO pad and the first node (implicit)(refer to fig.1), and being configured to clamp a second ESD event at the IO pad or the first node (refer to [0045]); however, Ishizuka does not teach a header circuit coupled between the first node and a third node, the header circuit coupled to a first voltage supply having a first supply voltage, and being configured to provide the first supply voltage to the first node in response to a control signal. However, Wertheimer teaches a header circuit (i.e. transistor P1)(fig.4) coupled between the first node (i.e. VIRTUAL VCC)(fig.4) and a third node (i.e. VCC)(fig.4), the header circuit coupled to a first voltage supply (refer to VCC)(fig.4) having a first supply voltage (implicit), and being configured to provide the first supply voltage to the first node in response to a control signal (refer to CTL)(fig.4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Ishizuka to include the header of Wertheimer to provide the advantage of disconnecting the circuit from power when it is not active.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizuka and Wertheimer as applied to claim 13 above, and further in view of Wang U.S. Patent Application 2021/0050341 (hereinafter “Wang”).
Regarding claim 14, Ishizuka and Wertheimer teach the integrated circuit of claim 13; however, they do not teach the integrated circuit further comprising: a third clamp circuit coupled between the third node and the second node. However, Wang teaches the integrated circuit further comprising: a third clamp circuit coupled between the third node and the second node (i.e. clamping circuit 130)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Ishizuka and Wertheimer to include the clamping circuits and capacitor of Wang to provide the advantage of providing paths to discharge ESD between each of the power rails, thereby preventing damage to the internal circuitry.
Regarding claim 15, Ishizuka, Wertheimer, and Wang teach the integrated circuit of claim 14, further comprising: a capacitor (i.e. Wang capacitor C)(fig.1) coupled between the first node and the second node (implicit); and an internal circuit (i.e. Ishizuka input circuit 39)(fig.1) coupled to the input of the buffer circuit (implicit).
Regarding claim 16, Ishizuka, Wertheimer, and Wang teach the integrated circuit of claim 15, further comprising: a fourth clamp circuit (i.e. Wang clamping circuit 120)(fig.1) coupled between the first node and the second node (implicit).
Allowable Subject Matter
Claims 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 17-19 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 17, especially wherein the first clamp circuit comprises: a first current mirror coupled to at least the IO pad, a first path and a second path; a first set of diodes serially coupled to each other, and being coupled to the first current mirror by the second path; a first resistor coupled to the second path, the first set of diodes, a fourth node and the second node; a first transistor of a first type, the first transistor including a first gate coupled to at least the fourth node and the first resistor, a first drain coupled to the IO pad, and a first source coupled to the second node; and a first diode including a first anode and a first cathode, the first anode being coupled to the IO pad, and the first cathode being coupled to the second node and the first resistor. Claims 18 and 19 are indicated as containing allowable subject matter based on their dependency on claim 17.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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