DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 1/3/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. CLAIM INTERPRETATION
Claim Interpretation - 35 USC ' 112 6th/f
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a temperature information analysis module configured to obtain temperature information regarding a plurality of memory cells included in the memory device” as recited in claims 1-7 and 14-20. The Examiner notes the corresponding structure and algorithm for this limitation corresponds to a ‘refresh processor’ or other processors as described in at least paragraph 20 and 33 of the Applicant’s specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schaefer (US 20200258566).
With respect to claim 1, the Schaefer reference teaches a memory device for performing refresh operations, the memory device comprising:
a refresh management circuit configured to perform refresh operations on the memory device based on a refresh command received from a host; (see fig. 3, refresh detection circuit 335; and paragraph 86, where refresh detection circuit 335 may receive an indication of when (e.g., based on a time, clock cycle, internal counter, or the like) refresh commands are received from host device 305. In some cases, refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold)
a counter configured to count a number of the refresh operations performed by the refresh management circuit; (paragraph 86, where refresh detection circuit 335 may receive an indication of when (e.g., based on a time, clock cycle, internal counter, or the like) refresh commands are received from host device 305. In some cases, refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold) and
a temperature information analysis module configured to obtain temperature information regarding a plurality of memory cells included in the memory device, (see fig. 3, temperature detection circuit 340; and paragraph 88, where refresh detection circuit 335 may be configured to determine one or more refresh thresholds stored at threshold storage 330 to use as an operative threshold based on a condition (e.g., temperature, host device commands, sensor outputs, etc.) of memory array 325, memory device 310, temperature detection circuit 340, or the like, or a combination thereof.) wherein the refresh management circuit is further configured to:
perform a predetermined number of the refresh operations during a first time period, based on determining that the predetermined number of the refresh operations are performed, (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold; and paragraph 86, where refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold)
receive the temperature information, (paragraph 90) and
adjust a refresh rate of the memory device for a second time period based on the temperature information. (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold)
With respect to claim 2, the Schaefer reference teaches the memory device of claim 1, wherein the counter is farther configured to activate a flag signal based on determining that the predetermined number of the refresh operations are performed, and wherein the refresh management circuit is farther configured to stop performing the refresh operations based on the flag signal being activated. (paragraph 104, where a host device may use the operative threshold to modify the rate [i.e. ‘stop’ as claimed] at which the host device sends refresh commands to the memory device. In some cases, a pin of the memory device may be used to signal the flag or threshold to a host device. For example, by driving a signal at the pin either high or low to indicate that the operative threshold is not satisfied. In some cases, more than one channel 115 may be used to signal the flag or threshold to a host device)
With respect to claim 3, the Schaefer reference teaches the memory device of claim 1, wherein the refresh management circuit is further configured to stop performing the refresh operations based on a command other than the refresh command being received. (paragraph 104, where a host device may use the operative threshold to modify the rate [i.e. ‘stop’ as claimed] at which the host device sends refresh commands to the memory device. In some cases, a pin of the memory device may be used to signal the flag or threshold to a host device. For example, by driving a signal at the pin either high or low to indicate that the operative threshold is not satisfied. In some cases, more than one channel 115 may be used to signal the flag or threshold to a host device)
With respect to claim 4, the Schaefer reference teaches the memory device of claim 3, wherein the refresh management circuit is further configured to reset the refresh rate after the refresh operations are stopped. (paragraph 106, where the host device may send a flag or other acknowledgement (e.g., command sequence or other signaling) to memory device. In some cases, the host device may send the signaling via a pin of the host device, through one or more commands (e.g., mode registry or access commands), through one or more channels (e.g., channels 115), or a combination thereof. Additionally or alternatively, the host device may transmit signaling to the memory device by sending a new set of refresh commands with a refresh rate that satisfies the operative threshold)
With respect to claim 5, the Schaefer reference teaches the memory device of claim 1, wherein the refresh management circuit is further configured to ignore the refresh command and adjust the refresh rate based on a change in the temperature information. (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold)
With respect to claim 6, the Schaefer reference teaches the memory device of claim 1, further comprising a flag signal controller configured to determine whether a command other than the refresh command is received. (paragraph 121, where the memory device may unlock a limited set of command options in response to receiving an acknowledgement from the host device at block 525. For example, the memory device may receive, process or carry out refresh commands to determine whether the host device is able to satisfy the operative threshold. The memory device may maintain a limited command set until the host device satisfies the operative threshold for one or more refresh cycles, upon which the memory may transition to block 505 and a full set of mode registry commands or access mode commands may be unlocked)
With respect to claim 7, the Schaefer reference teaches the memory device of claim 6, wherein, based on the command being received, the flag signal controller is further configured to transmit a flag reset signal to the counter, and transmit a refresh rate reset signal to the refresh management circuit. (paragraph 118, where if an acknowledgement (or in some cases, a command to exit the second mode and/or reset to the first mode) is received from the host device, the memory array may proceed to block 535 and may exit the second mode of operation. In some cases, a reset procedure may transition the memory array from the second mode of operation (e.g., safe mode) to the first mode of operation (e.g., a mission mode or access mode). The command to reset to the first mode may include a single command (e.g., acknowledgement), or a specific indication (e.g., the operative threshold) that may be known by the host device and by the memory device. The sequence may act as an acknowledgement)
Claims 8-13 are method implementation of claims 1-7, and rejected under the similar rationale as shown above.
Claims 14-20 are memory system implementation of claims 1-7, and rejected under the similar rationale as shown above. The Examiner notes claim 14 further includes “a host configured to generate a plurality of commands corresponding to the memory device” which is shown in fig. 3, host device 305, and corresponding text.
4. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
He (US 20200402569), which teaches a method that may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described;
Burke (US 20210263574), which teaches an information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module; and
Chin (US 20220147126), which teaches a memory of an information handling system may determine a memory test pattern for execution on the memory during a memory self-test procedure. The memory may execute the test pattern on the memory. While executing the test pattern on the memory, the memory may determine that a temperature of the memory has exceeded a predetermined temperature threshold. The memory may throttle execution of the test pattern based, at least in part, on the determination that the temperature of the memory has exceeded the first temperature threshold.
5. CLOSING COMMENTS
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137