DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 5/12/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schaefer (US 20200258566).
With respect to claim 1, the Schaefer reference teaches a memory device for performing refresh operations, the memory device comprising:
a refresh management circuit configured to perform refresh operations on the memory device based on a refresh command received from a host; (see fig. 3, refresh detection circuit 335; and paragraph 86, where refresh detection circuit 335 may receive an indication of when (e.g., based on a time, clock cycle, internal counter, or the like) refresh commands are received from host device 305. In some cases, refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold)
a counter configured to count a number of the refresh operations performed by the refresh management circuit; (paragraph 86, where refresh detection circuit 335 may receive an indication of when (e.g., based on a time, clock cycle, internal counter, or the like) refresh commands are received from host device 305. In some cases, refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold) and
wherein the refresh management circuit is further configured to:
perform a predetermined number of the refresh operations during a first time period, (paragraph 86, where refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold)
based on determining that the predetermined number of the refresh operations are performed, receive the temperature information regarding a plurality of memory cells included in the memory device, (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold; and paragraph 86, where refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold)
adjust a refresh rate of the memory device for a second time period based on the temperature information. (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold; paragraph 33, where memory system 110 may track, via OP[6] of the mode register 205-a, whether a refresh rate change (e.g., MR4 refresh rate) has occurred, where the refresh rate change may indicate that a temperature of the memory system 110 may be outside of a threshold temperature range, which may result in a refresh rate change and thus an MR4 register setting change)
With respect to claim 2, the Schaefer reference teaches the memory device of claim 1, wherein the counter is farther configured to activate a flag signal based on determining that the predetermined number of the refresh operations are performed, and wherein the refresh management circuit is farther configured to stop performing the refresh operations based on the flag signal being activated. (paragraph 104, where a host device may use the operative threshold to modify the rate [i.e. ‘stop’ as claimed] at which the host device sends refresh commands to the memory device. In some cases, a pin of the memory device may be used to signal the flag or threshold to a host device. For example, by driving a signal at the pin either high or low to indicate that the operative threshold is not satisfied. In some cases, more than one channel 115 may be used to signal the flag or threshold to a host device)
With respect to claim 3, the Schaefer reference teaches the memory device of claim 1, wherein the refresh management circuit is further configured to stop performing the refresh operations based on a command other than the refresh command being received. (paragraph 104, where a host device may use the operative threshold to modify the rate [i.e. ‘stop’ as claimed] at which the host device sends refresh commands to the memory device. In some cases, a pin of the memory device may be used to signal the flag or threshold to a host device. For example, by driving a signal at the pin either high or low to indicate that the operative threshold is not satisfied. In some cases, more than one channel 115 may be used to signal the flag or threshold to a host device)
With respect to claim 4, the Schaefer reference teaches the memory device of claim 3, wherein the refresh management circuit is further configured to reset the refresh rate after the refresh operations are stopped. (paragraph 106, where the host device may send a flag or other acknowledgement (e.g., command sequence or other signaling) to memory device. In some cases, the host device may send the signaling via a pin of the host device, through one or more commands (e.g., mode registry or access commands), through one or more channels (e.g., channels 115), or a combination thereof. Additionally or alternatively, the host device may transmit signaling to the memory device by sending a new set of refresh commands with a refresh rate that satisfies the operative threshold)
With respect to claim 5, the Schaefer reference teaches the memory device of claim 1, wherein the refresh management circuit is further configured to ignore the refresh command and adjust the refresh rate based on a change in the temperature information. (paragraph 90, where if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold)
With respect to claim 6, the Schaefer reference teaches the memory device of claim 1, further comprising a flag signal controller configured to determine whether a command other than the refresh command is received. (paragraph 121, where the memory device may unlock a limited set of command options in response to receiving an acknowledgement from the host device at block 525. For example, the memory device may receive, process or carry out refresh commands to determine whether the host device is able to satisfy the operative threshold. The memory device may maintain a limited command set until the host device satisfies the operative threshold for one or more refresh cycles, upon which the memory may transition to block 505 and a full set of mode registry commands or access mode commands may be unlocked)
With respect to claim 7, the Schaefer reference teaches the memory device of claim 6, wherein, based on the command being received, the flag signal controller is further configured to transmit a flag reset signal to the counter, and transmit a refresh rate reset signal to the refresh management circuit. (paragraph 118, where if an acknowledgement (or in some cases, a command to exit the second mode and/or reset to the first mode) is received from the host device, the memory array may proceed to block 535 and may exit the second mode of operation. In some cases, a reset procedure may transition the memory array from the second mode of operation (e.g., safe mode) to the first mode of operation (e.g., a mission mode or access mode). The command to reset to the first mode may include a single command (e.g., acknowledgement), or a specific indication (e.g., the operative threshold) that may be known by the host device and by the memory device. The sequence may act as an acknowledgement)
With respect to claim 21, the Schaefer reference teaches the memory device of claim 1, wherein the refresh management circuit is further configured to: perform at least one refresh operation during the second time period, and based on receiving a new command different from the reset command, stop performing the at least one refresh operation, and reset the refresh rate for a third time period, and wherein the counter is further configured to reset the count based on receiving the new command. (paragraph 33, where memory system 110 may track, via OP[6] of the mode register 205-a, whether a refresh rate change (e.g., MR4 refresh rate) has occurred, where the refresh rate change may indicate that a temperature of the memory system 110 may be outside of a threshold temperature range, which may result in a refresh rate change and thus an MR4 register setting change; and paragraph 38, where when the operands of the mode register 205-b are written to (e.g., set), the memory system 110 may reset the value of the operands of the mode register 205-b to the default values when the memory system 110 receives and applies a reset command or a power source is removed from the memory system 110. That is, the memory system 110 may retain the set values of the operands until the reset command is applied or power is removed (e.g., or the memory system 110 receives a MRW command to rewrite the operands to a different state).
Claims 8-13 are method implementation of claims 1-7 and 21, and rejected under the similar rationale as shown above.
Claims 14-20 are memory system implementation of claims 1-7 and 21, and rejected under the similar rationale as shown above. The Examiner notes claim 14 further includes “a host configured to generate a plurality of commands corresponding to the memory device” which is shown in fig. 3, host device 305, and corresponding text.
2. ARGUMENTS CONCERNING CLAIM INTERPRETATION
USC 112 f/6th Claim Interpretation
Applicant's amendments with respect to claims 1-7 and 14-20 have been considered and have overcome the Examiner’s prior interpretations and thus are withdrawn.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-12 of the remarks) and amendments with respect to claims 1-21 have been considered, but are not persuasive. The Applicant argues (see pages 8-12) the prior art does not explicitly teach the limitation of "based on determining that the predetermined number of the refresh operations are performed, receive temperature information regarding a plurality of memory cells included in the memory device, and adjust a refresh rate of the memory device for a second time period based on the temperature information". The Schaefer reference teaches (paragraph 86) a refresh detection circuit 335 may count the quantity of refresh commands received from host device 305 over the time window associated with the operative threshold and compare the counted quantity of refresh commands to a minimum quantity of refresh commands associated with (e.g., indicated in or otherwise specified for) the operative threshold. The Schaefer reference further teaches (paragraph 88) refresh detection circuit 335 may be configured to determine one or more refresh thresholds stored at threshold storage 330 to use as an operative threshold based on a condition (e.g., temperature, host device commands, sensor outputs, etc.) of memory array 325, memory device 310, temperature detection circuit 340, or the like, or a combination thereof; and further teaches (paragraph 90) if refresh detection circuit 335 determines that the refresh rates is equal to or above the threshold (e.g., satisfies the threshold), refresh detection circuit 335 may continue to monitor incoming refresh commands, and may in some cases update/adjust the operative refresh threshold based on one or more evolving conditions (e.g., the temperature) of the memory device 310, and determine whether refresh commands received from host device 305 satisfy the updated operative threshold. Lastly, the Schaefer reference teaches (paragraph 33) that the memory system 110 may track, via OP[6] of the mode register 205-a, whether a refresh rate change (e.g., MR4 refresh rate) has occurred, where the refresh rate change may indicate that a temperature of the memory system 110 may be outside of a threshold temperature range, which may result in a refresh rate change and thus an MR4 register setting change. Thus, based on the citations above, Schaefer teaches the refresh rate will change (i.e. being adjusted for a “second time period” [for operations after current operations]) based on the temperature of the memory being outside (i.e. above) a threshold. Therefore, the Examiner has maintained the rejections for the reasons set forth above. The Examiner notes any other arguments not specifically addressed can refer to the response above.
4. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Jung (US 20240203477), which teaches a memory device that includes: a rate control circuit configured to: generate a refresh counting value based on a refresh management command and an internal target refresh command, and generate a rate control signal by comparing the refresh counting value with a target value corresponding to temperature information; and a target command issuing circuit configured to: set a target number according to the rate control signal, and issue the internal target refresh command whenever a number of inputs of a normal refresh command reaches the target number.
5. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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