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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7, 9-10, and 13-14 of U.S. Patent No. 12,216,594. Although the claims at issue are not identical, they are not patentably distinct from each other as shown below:
Regarding claim 1, U.S. Patent No. 12,216,594 discloses:
An apparatus, comprising:
a communication bus configured to couple to a plurality of memory ranks, a given one of which includes a plurality of memory circuits (claim 1: a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus); and
a memory control circuit coupled to the communication bus and configured to (claim 1: a memory control circuit configured to):
receive a first set of read requests to a first memory rank of the plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks (claim 1: receive a plurality of read requests for the plurality of memory ranks, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks);
determine, for a read turn in which read requests are processed against the plurality of memory ranks, a number of rank switches to perform between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the first and second sets of read requests (claim 1: determine, for the read turn, a number of rank switches between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the plurality of read requests); and
process particular read requests of the first and second sets of read requests during the read turn using the number of rank switches (claim 1: perform allocated read requests during the read turn using the number of rank switches).
Regarding claim 2, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit is configured to limit, based on a determination that the at least one quality-of-service requirement is not satisfied, the number of rank switches to only one rank switch, and wherein, to process the particular read requests using the one rank switch (claim 3: wherein to determine the number of rank switches, the memory control circuit is further configured to limit the number of rank switches to one, in response to a determination that the real-time bandwidth quality-of-service requirement is not satisfied),
the memory control circuit is configured to:
process first ones of the first set of read requests against the first memory rank (claim 13: performing a first set allocated read requests associated with the initial memory rank);
in response to a completion of the first read requests, perform the one rank switch for the read turn from the first memory rank to the second memory rank (claim 13: in response to completing the first set allocated read requests associated with the initial memory rank, switching to a different memory rank of the first memory rank or the second memory rank); and
in response to a completion of the one rank switch, process second ones of the second set of read requests against the second memory rank (claim 13: performing a second set of allocated read requests associated with the different memory rank).
Regarding claim 3, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit is configured to include more than one rank switch in the number of rank switches in response to a determination that the at least one quality-of-service requirement is satisfied (claim 4: wherein to determine the number of rank switches, the memory control circuit is further configured to allow more than one rank switch, in response to a determination that the real-time bandwidth quality-of-service requirement is satisfied).
Regarding claim 4, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the at least one quality-of service requirement includes a real-time bandwidth quality-of-service requirement (claim 2: wherein in the at least one quality-of service requirement includes a real-time bandwidth quality-of-service requirement).
Regarding claim 5, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit configured to:
allocate, based on respective numbers of requests of the first and second sets and from a total number of slots corresponding to a total number of read requests processable during the read turn, a first number of slots of the total number of slots to read requests of the first set and a second number of slots of the total number of slots to read requests of the second set (claim 1: in response to an initiation of a read turn to the plurality of memory ranks, allocate, based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read requests included in the second subset).
Regarding claim 6, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit is further configured to:
select an initial memory rank of the first and second memory ranks based on which memory rank has an oldest low-latency quality-of-service read request pending (claim 5: select an initial memory rank of the first memory rank or the second memory rank based on which rank has an oldest low-latency quality-of-service read request pending); and
process the particular read requests starting with read requests that are associated with the initial memory rank (claim 5: perform the allocated read requests starting with a subset of the allocated read requests associated with the initial memory rank).
Regarding claim 7, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit is further configured to:
select an initial memory rank of the first and second memory ranks based on which memory rank has a larger number of low-latency quality-of-service read requests pending (claim 6: select an initial memory rank of the first memory rank and the second memory rank based on which rank has a largest number of low-latency quality-of-service read requests pending); and
process the particular read requests starting with read requests that are associated with the initial memory rank (claim 6: perform the allocated read requests starting with a subset of the allocated read requests associated with the initial memory rank).
Regarding claim 8, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, wherein the memory control circuit is further configured to:
select an initial memory rank of the first and second memory ranks based on which memory rank has a smaller number of low-latency quality-of-service read requests pending (claim 7: select an initial memory rank of the first memory rank and the second memory rank based on which rank has a smallest number of low-latency quality-of-service read requests pending); and
process the particular read requests starting with read requests that are associated with the initial memory rank (claim 7: perform the allocated read requests starting with a subset of the allocated read requests associated with the initial memory rank).
Regarding claim 9, U.S. Patent No. 12,216,594 further discloses:
The apparatus of claim 1, further comprising the plurality of memory ranks (claim 1: a plurality of memory ranks).
Regarding claim 10, U.S. Patent No. 12,216,594 discloses:
A method, comprising:
receiving, by a memory control circuit, a first set of read requests to a first memory rank of a plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks, wherein a given memory rank includes a plurality of memory circuits coupled to a common communication bus (claim 9: receiving, by a memory control circuit, a plurality of read requests for a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks);
determining, by the memory control circuit and based on a determination that at least one quality-of service requirement is not satisfied, to perform only one rank switch for a first read turn in which read requests are processed against the plurality of memory ranks (claim 9 determining, by the memory control circuit in response to an initiation of the read turn to the plurality of memory ranks, a number of rank switches between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the plurality of read requests; claim 10: wherein determining the number of rank switches includes setting, by the memory control circuit, the number of rank switches to one, in response to determining that the real-time bandwidth quality-of-service requirement is not satisfied);
processing, by the memory control circuit, first ones of the first set of read requests against the first memory rank during the first read turn (claim 13: performing a first set allocated read requests associated with the initial memory rank);
in response to completing the processing, the memory control circuit performing the one rank switch from the first memory rank to the second memory rank (claim 13: in response to completing the first set allocated read requests associated with the initial memory rank, switching to a different memory rank of the first memory rank or the second memory rank); and
in response to completing the rank switch, the memory control circuit processing second ones of the second set of read requests against the second memory rank during the first read turn (claim 13: performing a second set of allocated read requests associated with the different memory rank ).
Regarding claim 11, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, further comprising:
receiving, by the memory control circuit, a third set of read requests to the first memory rank and a fourth set of read requests to the second memory rank (claim 1: receive a plurality of read requests for the plurality of memory ranks, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks);
determining, by the memory control circuit and based on a determination that the at least one quality-of service requirement is satisfied, to perform a plurality of rank switches for a second read turn (claim 4: wherein to determine the number of rank switches, the memory control circuit is further configured to allow more than one rank switch, in response to a determination that the real-time bandwidth quality-of-service requirement is satisfied); and
processing, by the memory control circuit, read requests of the third and fourth sets of read requests during the second read turn using the plurality of rank switches (claim 1: perform allocated read requests during the read turn using the number of rank switches).
Regarding claim 12, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, further comprising:
in response to an initiation of the first read turn, the memory control circuit allocating, based on respective numbers of requests of the first and the second sets, a first number of slots of a total number of slots for the first read turn to read requests of the first set and a second number of slots of the total number of slots to read request of the second set (claim 9: allocating, by the memory control circuit and based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read request included in the second subset, wherein the total number of slots corresponds to a maximum number of read accesses that can be performed in a read turn).
Regarding claim 13, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, further comprising:
selecting, by the memory control circuit, the first memory rank as an initial memory rank to start with for the first read turn based on the first memory rank being associated with an older low-latency quality-of-service read request pending than the second memory rank (claim 13: selecting, by the memory control circuit, an initial memory rank of the first memory rank or the second memory rank based on which rank has an oldest low-latency quality-of-service read request pending).
Regarding claim 14, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, further comprising:
selecting, by the memory control circuit, the first memory rank as an initial memory rank to start with for the first read turn based on the first memory rank being associated with a larger number of low-latency quality-of-service read requests pending than the second memory rank (claim 14: selecting, by the memory control circuit, an initial memory rank of the first memory rank or the second memory rank based on which rank has a largest number of low-latency quality-of-service read requests pending).
Regarding claim 15, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, wherein the processing of the first read requests include:
selecting, by the memory control circuit, a read request from the first set of read requests in response to a determination that an age of the read request is greater than a threshold value (claim 5: select an initial memory rank of the first memory rank or the second memory rank based on which rank has an oldest low-latency quality-of-service read request pending); and
processing, by the memory control circuit, read request during the first read turn (claim 5: perform the allocated read requests starting with a subset of the allocated read requests associated with the initial memory rank).
Regarding claim 16, U.S. Patent No. 12,216,594 further discloses:
The method of claim 10, wherein the at least one quality-of service requirement includes a real-time bandwidth quality-of-service requirement (claim 2: wherein in the at least one quality-of service requirement includes a real-time bandwidth quality-of-service requirement).
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4, and 6 of U.S. Patent No. U.S. Patent No. 12,216,594 in view of Magudilu Vijavaraj et al. (10,838,884).
Regarding claim 17, U.S. Patent No. 12,216,594 discloses:
A system, comprising:
a plurality of memory ranks, a given one of which includes a plurality of memory circuits coupled to a common communication bus (claim 1: a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus);
…a memory control circuit configured to (claim 1: a memory control circuit configured to):
receive, from the at least one processor circuit, a first set of read requests to a first memory rank of the plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks (claim 1: receive a plurality of read requests for the plurality of memory ranks, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks);
process particular read requests of the first and second sets of read requests during a read turn using only one rank switch between the first and second memory ranks in response to a determination that at least one quality-of-service requirement associated with the first and second sets of read requests is not satisfied (claim 3: wherein to determine the number of rank switches, the memory control circuit is further configured to limit the number of rank switches to one, in response to a determination that the real-time bandwidth quality-of-service requirement is not satisfied; claim 1: perform allocated read requests during the read turn using the number of rank switches); and
process the particular read requests of the first and second sets during the read turn using a plurality of rank switches between the first and second memory ranks in response to a determination that the at least one quality-of-service requirement is satisfied (claim 4: wherein to determine the number of rank switches, the memory control circuit is further configured to allow more than one rank switch, in response to a determination that the real-time bandwidth quality-of-service requirement is satisfied; claim 1: perform allocated read requests during the read turn using the number of rank switches).
U.S. Patent No. 12,216,594 does not appear to explicitly claim “at least one processor circuit configured to issue memory requests, including read and write requests, directed to ones of the plurality of memory ranks.” However, Magudilu Vijavaraj et al. disclose:
at least one processor circuit configured to issue memory requests, including read and write requests, directed to ones of the plurality of memory ranks (Col 11, lines 54-56; memory access requests may include both memory read access requests and memory write access requests. Such access requests may be received from processor circuit 802); and
U.S. Patent No. 12,216,594 and Magudilu Vijavaraj et al. are analogous art because U.S. Patent No. 12,216,594 and Magudilu Vijavaraj et al. teach memory accessing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of U.S. Patent No. 12,216,594 and Magudilu Vijavaraj et al. before him/her, to modify U.S. Patent No. 12,216,594 with the processor circuit of Magudilu Vijavaraj et al. because such a modification would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.)
Regarding claim 18, U.S. Patent No. 12,216,594 further discloses:
The system of claim 17, wherein the memory control circuit is configured to allocate, from a total number of slots corresponding to a total number of read requests processable during the read turn, a first number of slots for read requests of the first set and a second number of slots for read request of the second set (claim 1: in response to an initiation of a read turn to the plurality of memory ranks, allocate, based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read requests included in the second subset).
Regarding claim 19, U.S. Patent No. 12,216,594 further discloses:
The system of claim 17, wherein the memory control circuit is configured to:
select an initial memory rank of the first and second memory ranks based on which memory rank has a larger number of low-latency quality-of-service read requests pending (claim 6: select an initial memory rank of the first memory rank and the second memory rank based on which rank has a largest number of low-latency quality-of-service read requests pending); and
process the particular read requests starting with read requests that are associated with the initial memory rank (claim 6: perform the allocated read requests starting with a subset of the allocated read requests associated with the initial memory rank).
Regarding claim 20, Magudilu Vijavaraj et al. further disclose:
The system of claim 17, further comprising:
at least one input/output circuit configured to issue read requests to the memory control circuit to access data from ones of the plurality of memory ranks and provide the accessed data to a peripheral device coupled to the at least one input/output circuit (Col 12, 8-10: Input/output circuits 903 may be configured to coordinate data transfer between computer system 900 and one or more peripheral devices).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim.
Yun et al. (US 2024/0289020) disclose a memory controller for controlling rank transitions for a plurality of memory ranks based on the states of readiness of each rank and whether the number of requests to a particular memory rank is greater than or equal to a threshold value. Yun et al. do not appear to explicitly teach determining, for a read turn, a number rank switches between a first memory rank and a second memory rank based on quality-of-service requirements for a plurality of read requests.
Fryman et al. (US 20240256283) disclose that traditional memory request scheduling schemes reduce rank switching and its associated latencies by prioritizing requests of the same type (i.e., all reads before writes), and then scheduling requests to the same rank together (i.e., all reads to rank0 before any reads to rank1). Fryman et al. further disclose a memory request scheduling scheme that prioritizes rank switching to allow for increased channel utilization in dual rank memory configurations. Fryman et al. do not appear to explicitly teach determining, for a read turn, a number rank switches between a first memory rank and a second memory rank based on quality-of-service requirements for a plurality of read requests.
Shen et al. (US 2022/0413759) disclose a memory controller for efficient rank switching that increases the average number of same-rank accesses picked from a command queue before a rank switch is necessary. The memory controller increases a memory access command window size according to both a depth of the command queue and a depth of a staging buffer, which enables a decrease to the number of rank switches during a sequence of accesses. Shen et al. do not appear to explicitly teach determining, for a read turn, a number rank switches between a first memory rank and a second memory rank based on quality-of-service requirements for a plurality of read requests.
Yang (US 2016/0306567) discloses a method of operation a memory device in which a memory path for accessing memory ranks is created based on the bandwidth required to be allocated for a memory request. Once a memory path is created, the memory request is fulfilled by performing a memory interleaving to the allocated ranks in the memory path. Yang does not appear to explicitly teach determining, for a read turn, a number rank switches between a first memory rank and a second memory rank based on quality-of-service requirements for a plurality of read requests.
Zheng et al. (US 2009/0248994) disclose a method of memory burst scheduling that groups multiple memory requests into multiple memory rank queues. Each rank queue contains the memory requests that target addresses within a corresponding memory rank. The method schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced. Zheng et al. do not appear to explicitly teach determining, for a read turn, a number rank switches between a first memory rank and a second memory rank based on quality-of-service requirements for a plurality of read requests.
The prior art of Yun et al., Fryman et al., Shen et al., Yang, and Zheng et al. when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 1, the prior art, alone or in combination, does not disclose the following highlighted limitations, as claimed, in combination with the other claimed limitations:
“An apparatus, comprising: a communication bus configured to couple to a plurality of memory ranks, a given one of which includes a plurality of memory circuits; and a memory control circuit coupled to the communication bus and configured to: receive a first set of read requests to a first memory rank of the plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks; determine, for a read turn in which read requests are processed against the plurality of memory ranks, a number of rank switches to perform between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the first and second sets of read requests; and process particular read requests of the first and second sets of read requests during the read turn using the number of rank switches.”
Regarding claim 10, the prior art, alone or in combination, does not disclose the following highlighted limitations, as claimed, in combination with the other claimed limitations:
“A method, comprising: receiving, by a memory control circuit, a first set of read requests to a first memory rank of a plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks, wherein a given memory rank includes a plurality of memory circuits coupled to a common communication bus; determining, by the memory control circuit and based on a determination that at least one quality-of service requirement is not satisfied, to perform only one rank switch for a first read turn in which read requests are processed against the plurality of memory ranks; processing, by the memory control circuit, first ones of the first set of read requests against the first memory rank during the first read turn; in response to completing the processing, the memory control circuit performing the one rank switch from the first memory rank to the second memory rank; and in response to completing the rank switch, the memory control circuit processing second ones of the second set of read requests against the second memory rank during the first read turn.”
Regarding claim 17, the prior art, alone or in combination, does not disclose the following highlighted limitations, as claimed, in combination with the other claimed limitations:
“A system, comprising: a plurality of memory ranks, a given one of which includes a plurality of memory circuits coupled to a common communication bus; at least one processor circuit configured to issue memory requests, including read and write requests, directed to ones of the plurality of memory ranks; and a memory control circuit configured to: receive, from the at least one processor circuit, a first set of read requests to a first memory rank of the plurality of memory ranks and a second set of read requests to a second memory rank of the plurality of memory ranks; process particular read requests of the first and second sets of read requests during a read turn using only one rank switch between the first and second memory ranks in response to a determination that at least one quality-of-service requirement associated with the first and second sets of read requests is not satisfied; and process the particular read requests of the first and second sets during the read turn using a plurality of rank switches between the first and second memory ranks in response to a determination that the at least one quality-of-service requirement is satisfied.”
Claims 2-9, 11-16, and 18-20 are allowed based on their dependency from allowed base claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/TRACY A WARREN/Primary Examiner, Art Unit 2137