DETAILED ACTION
This is in response to the application filed on January 3, 2025 in which claims 21 – 40 are presented for examination (after preliminary amendment of January 3, 2025).
Status of Claims
Claims 21 – 40 are pending, of which claims 21, 27, and 34 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/6/2025, 3/28/2025, and 5/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the abstract refers to “a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer.” The disclosure refers to “TLB” and “TLBI” instruction throughout as being a “translation lookaside buffer” and “translation lookaside buffer invalidate” instruction, respectively. The term “translation lookaside buffer” is the commonly used term in the art. The examiner recommends amending the Abstract to refer to “a translation lookaside buffer invalidate (TLBI) instruction to invalidate an entry of a translation lookaside buffer.” A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 33 and 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 33 and 40 both refer to performing, by the processor responsive to receiving the other indication of the other DSB instruction, an instruction synchronization barrier (ISB) operation. However, Applicant’s disclosure describes “a processor may use synchronization barrier instructions, such as instruction synchronization barrier (ISB) and data synchronization barrier (DSB) instructions, to enforce ordering constraints” ([0003] of Applicant’s PGPub 2025/0147767) and “sometimes, an DSB instruction may be used in combination with an ISB instruction in a software program. For example, an ISB instruction may follow an DSB instruction in a software program, two of which collectively ensure ordering constraints on both instructions and memory accesses” ([0058] of Applicant’s PGPub 2025/0147767).
It is unclear how a DSB instruction causes an ISB response, as claimed in claims 33 and 40.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21 – 32 and 34 – 39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 3, 5 – 10, 12 – 17, and 19 of U.S. Patent No. 12,229,561 in view of Carlson, U.S. Patent Application 2020/0097292.
As shown below, the claims of the instant application differ from the claims of U.S. 12,229,561 in that 1) instant claim 21 clarifies that the DSB instruction is received from another processor and 2) the DSB instruction follows a cache invalidate instruction in the instant application vs the DSB instruction follows a TLB invalidate instruction in 12,229,561.
As seen in Carlson, an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches, and a TLB invalidate (TLBI) instruction can be used to invalidate entries in a TLB ([0017]). Further, "the local core that initiated a set of one or more invalidation instructions (e.g., a combination of TLBI and ICI instructions) is able to issue a data synchronization barrier (DSB) instruction after the set of invalidation instructions to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor)" ([0019]).
It is seen that the examined application claims would have been obvious over the reference claims.
12,229,561
19/009790
1. A processor, comprising: one or more circuits configured to implement an instruction pipeline, wherein the instruction pipeline is configured to: receive an
indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation lookaside buffer invalidate (TLBI) instruction to invalidate an entry of a translation lookaside buffer;
responsive to receiving the indication of the DSB instruction, determine whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
responsive to a determination that the instruction is pending, determine whether the instruction retires; and
responsive to a determination that the instruction retires, provide an acknowledgement to the other processor in response to the indication of the DSB instruction.
21. A processor, comprising: one or more circuits configured to implement an instruction pipeline configured to:
receive, from another processor, an indication of a data synchronization barrier (DSB) instruction in the other processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor;
determine, responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
determine, responsive to determining that the other instruction is pending, whether the other instruction retires; and
provide, responsive to determining that the other instruction retires, an acknowledgement to the other processor in response to the indication of the DSB instruction.
2. The processor of claim 1, wherein to determine whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address receiving the indication of the DSB instruction, the instruction pipeline is configured to: assign a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and is assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and compare the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
3. The processor of claim 2, wherein the instruction pipeline is configured to change the value of the second bit to the second value after providing the acknowledgement to the other processor in response to the indication of the DSB instruction.
5. The processor of claim 1, wherein
the instruction pipeline is
configured to: receive another indication of another DSB instruction in the other processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and responsive to a determination that the other instruction is pending, flush instructions younger than the additional DSB from the instruction pipeline.
6. The processor of claim 1, wherein
the instruction pipeline is configured to:
receive another indication of another DSB instruction in the other processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an instruction in the processor to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the processor; and responsive to a determination that the other instruction is pending, flush instruction younger than the PCIe instruction from the instruction pipeline.
7. The processor of claim 1, wherein the instruction pipeline is configured to:
receive another indication of another DSB instruction in the other processor that follows an instruction cache invalidate (TLBI) instruction to invalidate an instruction of an instruction cache; and
responsive to receipt of the other indication of the other DSB instruction, flush an instruction pipeline of the processor.
22. The processor of claim 21, wherein to determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address,
the
instruction pipeline is configured to: assign a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and is assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and compare the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
23. The processor of claim 22, wherein the instruction pipeline is configured to change the value of the second bit to the second value after providing the acknowledgement to the other processor in response to the indication of the DSB instruction.
24. The processor of claim 21, wherein the instruction pipeline is further configured to: receive another indication of another DSB instruction in the other processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and flush, responsive to a determination that the other instruction is pending, instructions younger than the additional DSB from the instruction pipeline.
25. The processor of claim 21, wherein the instruction pipeline is further configured to:
receive another indication of another DSB instruction in the other processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an instruction in the processor to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the processor; and flush, responsive to a determination that the other instruction is pending, instruction younger than the PCIe instruction from the instruction pipeline.
26. The processor of claim 21, wherein the instruction pipeline is further configured to:
receive another indication of another DSB instruction in the other processor that follows another cache invalidate instruction; and
flush, responsive to receipt of the other indication of the other DSB instruction, an instruction pipeline of the processor.
8. A method, comprising:
receiving, by a processor from another processor, an indication of a data synchronization barrier (DSB) in an instruction that follows a translation lookaside buffer invalidate (TLBI) instruction to invalidate an entry of a translation lookaside buffer;
determining, by the processor responsive to receiving the indication of the DSB instruction, whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
responsive to determining that the instruction is pending, determining, by the processor, whether the instruction retires; and
responsive to determining that the instruction retires, providing, by the processor, an acknowledgement to the other processor in response to the indication of the DSB instruction.
27. A method, comprising:
receiving, by a processor from another processor, an indication of a data synchronization barrier (DSB) instruction in the other processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor;
determining, by the processor responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address; and
responsive to determining that the other instruction is pending, determining, by the processor, whether the other instruction retires; and
responsive to determining that the other instruction retires, providing, by the processor, an acknowledgement to the other processor in response to the indication of the DSB instruction.
9. The method of claim 8, wherein determining whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address is translated before receiving the indication of the DSB instruction comprises:
assigning a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and comparing the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
10. The method of claim 9, further comprising changing
the value of the second bit to the second value after providing the acknowledgement to the other processor in response to the indication of the DSB instruction.
12. The method of claim 8, further comprising: receiving, by the processor,
another indication of another DSB instruction in the other processor;
determining, by the processor, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and
responsive to determining that the other instruction is pending, flushing, by the processor, instructions younger than the additional DSB from an instruction pipeline of the processor.
13. The method of claim 8, further comprising: receiving, by the processor,
another indication of another DSB instruction in the other processor; determining, by the processor, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an instruction in the processor to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the processor; and
responsive to determining that the other instruction is pending, flushing, by the processor, instruction younger than the PCIe instruction from an instruction pipeline of the processor.
14. The method of claim 8, further comprising: receiving, by the processor,
another indication of another DSB instruction in the other processor that follows an instruction cache invalidate (TLBI) instruction to invalidate an instruction of an instruction cache; and
responsive to receiving the other indication of the other DSB instruction, flushing, by the processor, an instruction pipeline of the processor.
28. The method of claim 27, wherein determining whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address comprises:
assigning a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and is assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and comparing the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
29. The method of claim 28, further comprising changing, by the processor, the value of the second bit to the second value after providing the acknowledgement to the other processor in response to the indication of the DSB instruction.
30. The method of claim 27, further comprising: receiving, by the processor from the other processor,
another indication of another DSB instruction in the other processor;
determining, by the processor, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and
flushing, by the processor responsive to a determination that the other instruction is pending, instructions younger than the additional DSB from the instruction pipeline.
31. The method of claim 27, further comprising: receiving, by the processor from the other processor,
another indication of another DSB instruction in the other processor; determining, by the processor, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an instruction in the processor to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the processor; and
flushing, by the processor responsive to a determination that the other instruction is pending, instruction younger than the PCIe instruction from the instruction pipeline.
32. The method of claim 27, further comprising: receiving, by the processor from the other processor,
another indication of another DSB instruction in the other processor that follows another cache invalidate instruction; and
flushing, by the processor responsive to receipt of the other indication of the other DSB instruction, an instruction pipeline of the processor.
15. A device, comprising: a first processor; a second processor; and memory storing program instructions, wherein the first processor comprises one or more circuits configured to implement an instruction pipeline, wherein the instruction pipeline is configured to: receive an
indication of a data synchronization barrier (DSB) instruction following a translation lookaside buffer invalidate (TLBI) instruction in the second processor;
responsive to receiving the indication of the DSB instruction, determine whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
responsive to a determination that the instruction is pending, determine whether the instruction retires; and
responsive to a determination that the instruction retires, provide an acknowledgement to the other processor in response to the indication of the DSB instruction.
34. A device, comprising: a first processor; a second processor; and memory storing program instructions; wherein the first processor comprises one or more circuits configured to implement an instruction pipeline, the instruction pipeline configured to:
receive, from the second processor, an
indication of a data synchronization barrier (DSB) instruction in the second processor that follows a cache invalidate instruction, wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the second processor;
determine, responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address;
determine, responsive to determining that the other instruction is pending, whether the other instruction retires; and
provide, responsive to determining that the other instruction retires, an acknowledgement to the second processor in response to the indication of the DSB instruction.
16. The device of claim 15, wherein to determine whether an instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the indication of the DSB instruction, the instruction pipeline is configured to: assign a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and is assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and compare the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
17. The device of claim 16, wherein the instruction pipeline is configured to change the value of the second bit to the second value after providing the acknowledgement to the second processor in response to the indication of the DSB instruction.
19. The device of claim 15, wherein the instruction pipeline is configured to:
receive another indication of the second DSB instruction in the second processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the first processor after receiving the other indication of the other DSB instruction; and
responsive to a determination that the other instruction is pending, flush instructions younger than the additional DSB from the instruction pipeline.
20. The device of claim 15, wherein the instruction pipeline is configured to:
receive another indication of another DSB instruction in the second processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an instruction that is fetched or decoded
in the first processor after receiving the other indication of the other DSB instruction
to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the first processor; and responsive to a determination that the other instruction is pending, flush instructions younger than the PCIe instruction from the instruction pipeline.
7. The processor of claim 1, wherein the instruction pipeline is configured to:
receive another indication of another
DSB instruction in the other processor that follows an instruction cache invalidate (TLBI) instruction to invalidate an instruction of an instruction cache; and
responsive to receipt of the other indication of the other DSB instruction, flush an instruction pipeline of the processor.
35. The device of claim 34, wherein to determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address,
the
instruction pipeline is configured to: assign a value to a first bit corresponding to the instruction, wherein the first bit is assigned a first value when the virtual address of the instruction is translated before receiving the indication of the DSB instruction, and is assigned a second value when the virtual address is not translated before receiving the indication of the DSB instruction; and compare the assigned value of the first bit corresponding to the instruction with a value of a second bit to determine whether the virtual address of the instruction has been translated before receiving the indication of the DSB instruction, wherein the second bit is assigned the first value.
36. The device of claim 35, wherein the instruction pipeline is configured to change the value of the second bit to the second value after providing the acknowledgement to the second processor in response to the indication of the DSB instruction.
37. The device of claim 34, wherein the instruction pipeline is further configured to:
receive another indication of another DSB instruction in the second processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the first processor after receiving the other indication of the other DSB instruction; and
flush, responsive to a determination that the other instruction is pending, instructions younger than the additional DSB from the instruction pipeline.
38. The device of claim 34, wherein the instruction pipeline is further configured to:
receive another indication of another DSB instruction in the second processor; determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction, wherein the other instruction
is younger than an instruction
in the processor
to cause loading of data through a Peripheral Component Interconnect Express (PCIe) interface of the first processor; and flush, responsive to a determination that the other instruction is pending, instruction younger than the PCIe instruction from the instruction pipeline.
39. The device of claim 34, wherein the instruction pipeline is further configured to: receive another indication of another DSB instruction in the second processor that follows another cache invalidate instruction; and
flush, responsive to receipt of the other indication of the other DSB instruction, an instruction pipeline of the first processor.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 27, and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Carlson et al., U.S. Patent 2020/0097292 (hereinafter referred to as Carlson).
Referring to claim 21, Carlson discloses “A processor, comprising: one or more circuits configured to implement an instruction pipeline” (Fig. 1 processor core 102 with pipeline 104) “configured to: receive, from another processor, an indication of a data synchronization barrier (DSB) instruction in the other processor that follows a cache invalidate instruction” ([0017] “an instruction set architecture may provide different types of invalidation instructions that are broadcast among the cores” and “an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches.” [0019] "the local core that initiated a set of one or more invalidation instructions (e.g., a combination of TLBI and ICI instructions) is able to issue a data synchronization barrier (DSB) instruction after the set of invalidation instructions to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor)"), “wherein execution of the cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor” ([0012] “The control circuitry is coupled to a message buffer for storing messages to be sent over interconnection circuitry that interconnects the plurality of processors, and the message buffer is used for storing messages for managing the translation lookaside buffer and is used for storing messages for accessing the cache module.” [0017] “an instruction set architecture may provide different types of invalidation instructions that are broadcast among the cores” and “an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches”); “determine, responsive to receiving the indication of the DSB instruction, whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address; determine, responsive to determining that the other instruction is pending, whether the other instruction retires; and provide, responsive to determining that the other instruction retires, an acknowledgement to the other processor in response to the indication of the DSB instruction” ([0019] data synchronization barrier (DSB) instruction sent after TLBI and ICI instructions “to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor).” [0003] virtual to physical address translation. [0045] “there may also be other communication that involves both broadcast messages and acknowledgement messages” and the “Global Sync message may ensure for each processor core that all outstanding load and store instructions have completed, and any TLBI instructions have been handled, before responding with an acknowledgement message from that processor core”).
Referring to claim 27, claim 21 recites the corresponding limitations as that of claim 27. Therefore, the rejection of claim 21 applies to claim 27.
Referring to claim 34, claim 21 recites the corresponding limitations as that of claim 34. Therefore, the rejection of claim 21 applies to claim 34.
Further, Carlson discloses “A device, comprising: a first processor; a second processor” (Fig. 1 system 100 with processor cores 102 of a multi-core architecture); “and memory storing program instructions; wherein the first processor comprises one or more circuits configured to implement an instruction pipeline, the instruction pipeline configured to” carry out the features of claim 21 (Fig. 1 and [0025] – [0026] pipeline 104 and memory system 108 with instruction cache).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24, 26, 30, 32, 37, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Carlson in view of Dooley et al., U.S. Patent Application 2021/0026632 (hereinafter referred to as Dooley) (from Applicant’s IDS).
As per claim 24, Carlson discloses “the instruction pipeline is further configured to: receive another indication of another DSB instruction in the other processor” ([0017] “an instruction set architecture may provide different types of invalidation instructions that are broadcast among the cores” and “an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches.” [0019] "the local core that initiated a set of one or more invalidation instructions (e.g., a combination of TLBI and ICI instructions) is able to issue a data synchronization barrier (DSB) instruction after the set of invalidation instructions to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor)"); “determine whether another instruction is pending for which a virtual address used for a memory access has been translated to a physical address before receiving the other indication of the other DSB instruction” ([0019] data synchronization barrier (DSB) instruction sent after TLBI and ICI instructions “to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor).” [0003] virtual to physical address translation. [0045] “there may also be other communication that involves both broadcast messages and acknowledgement messages” and the “Global Sync message may ensure for each processor core that all outstanding load and store instructions have completed, and any TLBI instructions have been handled, before responding with an acknowledgement message from that processor core”).
Further, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, it would have been obvious to have a second DSB instruction and another pending instruction with the same, expected results.
Carlson does not appear to explicitly disclose “the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and flush, responsive to a determination that the other instruction is pending, instructions younger than the additional DSB from the instruction pipeline.”
However, Dooley discloses “wherein the other instruction is younger than an additional DSB instruction that is fetched or decoded in the processor after receiving the other indication of the other DSB instruction; and flush, responsive to a determination that the other instruction is pending, instructions younger than the additional DSB from the instruction pipeline” ([0118] “a DSB with age 3 is issued by the issue circuitry 404. In response, the control circuitry 602 checks the RAR buffer 402 for any entries which are younger than the DSB” and “the control circuitry 602 sends control signals to trigger the pipeline to flush and to re-issue any load operations younger than age 3”).
Carlson and Dooley are analogous art because they are from the same field of endeavor, which is data synchronization methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlson and Dooley before him or her, to modify the teachings of Carlson to include the teachings of Dooley so that when another instruction is younger than an additional DSB instruction, the younger instructions are flushed.
The motivation for doing so would have been to maintain memory coherency while removing altered data from the pipeline (as stated by Dooley at [0084] – [0085] and [0121]).
Therefore, it would have been obvious to combine Dooley with Carlson to obtain the invention as specified in the instant claim.
As per claim 26, Carlson discloses “the instruction pipeline is further configured to: receive another indication of another DSB instruction in the other processor that follows another cache invalidate instruction” ([0017] “an instruction set architecture may provide different types of invalidation instructions that are broadcast among the cores” and “an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches.” [0019] "the local core that initiated a set of one or more invalidation instructions (e.g., a combination of TLBI and ICI instructions) is able to issue a data synchronization barrier (DSB) instruction after the set of invalidation instructions to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor)").
Further, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, it would have been obvious to have a second DSB instruction that follows another cache invalidate instruction with the same, expected results.
Carlson does not appear to explicitly disclose “and flush, responsive to receipt of the other indication of the other DSB instruction, an instruction pipeline of the processor.”
However, Dooley discloses “and flush, responsive to receipt of the other indication of the other DSB instruction, an instruction pipeline of the processor” ([0118] “a DSB with age 3 is issued by the issue circuitry 404. In response, the control circuitry 602 checks the RAR buffer 402 for any entries which are younger than the DSB” and “the control circuitry 602 sends control signals to trigger the pipeline to flush and to re-issue any load operations younger than age 3”).
Carlson and Dooley are analogous art because they are from the same field of endeavor, which is data synchronization methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlson and Dooley before him or her, to modify the teachings of Carlson to include the teachings of Dooley so that when another instruction is younger than an additional DSB instruction, the younger instructions are flushed.
The motivation for doing so would have been to maintain memory coherency while removing altered data from the pipeline (as stated by Dooley at [0084] – [0085] and [0121]).
Therefore, it would have been obvious to combine Dooley with Carlson to obtain the invention as specified in the instant claim.
Note, claim 30 recites the corresponding limitations of claim 24. Therefore, the rejection of claim 24 applies to claim 30.
Note, claim 32 recites the corresponding limitations of claim 26. Therefore, the rejection of claim 26 applies to claim 32.
Note, claim 37 recites the corresponding limitations of claim 24. Therefore, the rejection of claim 24 applies to claim 37.
Note, claim 39 recites the corresponding limitations of claim 26. Therefore, the rejection of claim 26 applies to claim 39.
Claims 33 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Carlson in view of Johar et al., U.S. Patent Application 2017/0286116 (hereinafter referred to as Johar) (from Applicant’s IDS).
As per claim 33, Carlson discloses “receiving, by the processor from the other processor, another indication of another DSB instruction in the other processor that follows another a cache invalidate instruction, wherein execution of the other cache invalidate instruction invalidates one or more instructions from an instruction cache of the other processor” ([0017] “an instruction set architecture may provide different types of invalidation instructions that are broadcast among the cores” and “an instruction cache invalidate (ICI) instruction can be used to invalidate entries in instruction caches.” [0019] "the local core that initiated a set of one or more invalidation instructions (e.g., a combination of TLBI and ICI instructions) is able to issue a data synchronization barrier (DSB) instruction after the set of invalidation instructions to ensure that the effect of those invalidation instructions have been globally observed (i.e., have taken effect at all cores in the processor)")
Further, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, it would have been obvious to have a second DSB instruction that follows another cache invalidate instruction with the same, expected results.
As above regarding 35 USC 112, the following claim limitation is unclear. In an attempt to advance prosecution, the examiner will treat this claim limitation as best understood.
Carlson does not appear to explicitly disclose “performing, by the processor responsive to receiving the other indication of the other DSB instruction, an instruction synchronization barrier (ISB) operation.”
However, Johar discloses “performing, by the processor responsive to” an ISB instruction, “an instruction synchronization barrier (ISB) operation” (Fig. 3 steps 52 to 72, ISB instruction causes ISB processing).
It would have been obvious to one of ordinary skill in the art to combine Johar’s ISB processing with the multiple processor system of Carlson so that a method includes “performing, by the processor responsive to receiving the other indication of the other [DSB] instruction, an instruction synchronization barrier (ISB) operation.”
Carlson and Johar are analogous art because they are from the same field of endeavor, which is synchronization methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlson and Johar before him or her, to modify the teachings of Carlson to include the teachings of Johar so that a received instruction causes an instruction synchronization barrier operation.
The motivation for doing so would have been to avoid executing old versions of program instructions which may still be pending in the pipeline (as stated by Johar at [0062]).
Therefore, it would have been obvious to combine Johar with Carlson to obtain the invention as specified in the instant claim.
Note, claim 40 recites the corresponding limitations of claim 33. Therefore, the rejection of claim 33 applies to claim 40.
Allowable Subject Matter
Claims 22, 23, 25, 28, 29, 31, 35, 36, and 38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Note that other issues exist as well, such as double patenting issues.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patents 12,229,561 and 12,639,070 are also to Applicant with similar teachings.
U.S. Patent Applications 20040215898, 20160283245, 20210173657, 20220229667, 20240320160, 20250130953 and Patents 6119204, 9501425, 9710394, 11194584, 11263015, 11732647, 11379379, 11403101, 11487874, 11500779, 11604873, 11663130, 11720360, 11822652, 11886882, 12204904, 12321746, 12346264, 12541461 teach remote DSB instructions.
U.S. Patent Applications 20200133680, 20210011729 and Patents 10817300, 11327759, 12293190 teach instruction cache invalidation and remote DSB instructions.
Contact Information
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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