DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/11/2025 and 01/03/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu, (U.S. Patent Application Publication No. 20250201651 A1), [hereinafter Liu], and further in view of Zheng (CN 115244685A using English translation), [hereinafter Zheng].
Regarding claim 1, Liu discloses an electronic device (Fig. 1) comprising:
a first substrate comprising a first surface and a second surface opposite to the first surface (Fig. 1, element 101 has a first and opposite second surface);
a second substrate comprising a third surface facing the first surface and a fourth surface opposite to the third surface (Fig. 1, element 105 has a first and opposite second surface 105A and B);
at least one interposer between the first surface and the third surface and electrically connecting the first substrate and the second substrate (Fig. 1 element S; and [0025] the system board 101 may be bonded to another substrate using external connections (not shown), which may be solder balls or other suitable conductive connections);
a first electronic component on the fourth surface (Fig. 1, element 107); and
a heat dissipation member (Fig. 1 element 220; and [0047] The double-sided heat dissipation module 200 also includes a second (or lower) heat spreader 220 located below the 3D-IC package module 103 (e.g., located on the side of the 3D-IC package module 103 near the second package components 109), as shown in FIG. 1. ) when viewed in a direction orthogonal to the fourth surface (Fig. 1 showing 220 is above 101, below 105, adjacent to S, and overlapping 107).
However, Liu does not explicitly disclose being in a solid phase at room temperature.
Zheng suggests being in a solid phase at room temperature (when selecting the filling material 70 and the thermal interface material layer 40 of the material combination, the melting point of the filling material 70 can be higher than the melting point of the thermal interface material layer 40, and the filling material 70 melting point higher than the reflow soldering of the welding point near the temperature, for example, filling material 70 is silica gel, The thermal interface material layer 40 is made of metal indium. when the substrate 10 is installed on the substrate 10 by means of FCBGA, it needs to use reflow soldering process, the temperature of the metal indium is heated to more than 200 ° C, the metal indium melting point is lower (generally about 156.61 ° C) to melt, but the melting point of the silica gel is high, will not melt, so as to, Although the metal indium is melted, it is still limited by the silica gel flow range, holding the good heat contact the chip 20 and the heat conducting cover 301. When the melting point of the filling material 70 is higher than the melting point of the thermal interface material layer 40, other materials can be combined, and the similar effect can be achieved).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu with the well-known silica gel material suggested by Zheng. The motivation would be to limit the flow of metal using the gel. Zheng at p. 11.
Regarding Claim 2, Liu-Zheng recites all the limitations of claim 1, as discussed above. However, Zheng also suggests wherein the heat dissipation member is in a gel phase within a temperature range above a softening point higher than room temperature (when selecting the filling material 70 and the thermal interface material layer 40 of the material combination, the melting point of the filling material 70 can be higher than the melting point of the thermal interface material layer 40, and the filling material 70 melting point higher than the reflow soldering of the welding point near the temperature, for example, filling material 70 is silica gel, The thermal interface material layer 40 is made of metal indium. when the substrate 10 is installed on the substrate 10 by means of FCBGA, it needs to use reflow soldering process, the temperature of the metal indium is heated to more than 200 ° C, the metal indium melting point is lower (generally about 156.61 ° C) to melt, but the melting point of the silica gel is high, will not melt, so as to, Although the metal indium is melted, it is still limited by the silica gel flow range, holding the good heat contact the chip 20 and the heat conducting cover 301. When the melting point of the filling material 70 is higher than the melting point of the thermal interface material layer 40, other materials can be combined, and the similar effect can be achieved).
Regarding Claim 3, Liu-Zheng recites all the limitations of claim 2, as discussed above. Zheng also suggests further comprising a solder electrically connecting the at least one interposer with the first substrate or the second substrate, wherein the heat dissipation member is configured to maintain being in the gel phase at a melting point of the solder which is higher than the softening point (when selecting the filling material 70 and the thermal interface material layer 40 of the material combination, the melting point of the filling material 70 can be higher than the melting point of the thermal interface material layer 40, and the filling material 70 melting point higher than the reflow soldering of the welding point near the temperature, for example, filling material 70 is silica gel, The thermal interface material layer 40 is made of metal indium. when the substrate 10 is installed on the substrate 10 by means of FCBGA, it needs to use reflow soldering process, the temperature of the metal indium is heated to more than 200 ° C, the metal indium melting point is lower (generally about 156.61 ° C) to melt, but the melting point of the silica gel is high, will not melt, so as to, Although the metal indium is melted, it is still limited by the silica gel flow range, holding the good heat contact the chip 20 and the heat conducting cover 301. When the melting point of the filling material 70 is higher than the melting point of the thermal interface material layer 40, other materials can be combined, and the similar effect can be achieved.).
Regarding Claim 4, Liu-Zheng recites all the limitations of claim 1, as discussed above. Liu also discloses further comprising at least one second electronic component on the third surface of the second substrate (Fig. 1, elements 109 and Fig. 2 element 105), wherein the heat dissipation member comprises a contacting portion which contacts at least one of the third surface or the at least one second electronic component (Fig. 1, element 220 contacts 109 and Fig. 2 105).
Regarding Claim 5, Liu-Zheng recites all the limitations of claim 4, as discussed above. Liu also discloses wherein the at least one second electronic component comprises a plurality of decoupling capacitors ([0028] In some embodiments, the substrate 105 may include conductive pads, conductive routing, and through substrate vias (TSVs) (not shown). The conductive routing may provide electrical interconnections, and may electrically couple the conductive pads and the TSVs. The conductive routing may include one or more layers of conductive lines, conductive vias, redistribution layers, metallization patterns, or the like. In some embodiments, the substrate 105 may or may not include active and/or passive components (e.g., transistors, diodes, resistors, capacitors, and the like)) between the heat dissipation member and the first electronic component and electrically connected to the first electronic component via the second substrate, wherein the contacting portion of the heat dissipation member is between the plurality of decoupling capacitors and contacts the third surface ([0027] The substrate 105 is used to interconnect the first package components 107 and the second package components 109 on both sides of the substrate 105. In some embodiments, the substrate 105 may be a semiconductor substrate, which may be a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, a multi-layered semiconductor substrate, or the like. The semiconductor material of the substrate 105 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The substrate 105 may be doped or undoped. [0028] In some embodiments, the substrate 105 may include conductive pads, conductive routing, and through substrate vias (TSVs) (not shown). The conductive routing may provide electrical interconnections, and may electrically couple the conductive pads and the TSVs. The conductive routing may include one or more layers of conductive lines, conductive vias, redistribution layers, metallization patterns, or the like. In some embodiments, the substrate 105 may or may not include active and/or passive components (e.g., transistors, diodes, resistors, capacitors, and the like). [0029] In some embodiments, the first package components 107 (also referred to herein as first IC devices) may include a plurality of high-performance semiconductor dies, which may be used for processing of 3D smart internet TV graphics or other processing intense applications, for example. In some embodiments, the first package components 107 may include processor (e.g., central processing unit (CPU), graphic processing unit (CPU), etc.) dies, memory (e.g., dynamic random access memory (DRAM), high bandwidth memory (HBM), memory stacks, etc.) dies, or other suitable semiconductor IC dies. The first package components 107 may all be the same type of package components having an identical structure, or may include a plurality of different types of package components. In addition, the first package components 107 may or may not have the same dimensions (e.g., height in the z-direction and/or area in the x-y plane).
Regarding Claim 6, Liu-Zheng recites all the limitations of claim 4, as discussed above. Liu also discloses further comprising a third electronic component on the first surface of the first substrate and at least partially covered by the heat dissipation member (Fogs. 1 and 2).
Regarding Claim 13, Liu-Zheng recites all the limitations of claim 1, as discussed above. Liu also discloses an adhesive member between the first surface of the first substrate and the heat dissipation member ([0061] FIG. 1 further illustrates that the 3D-IC package module 103 includes an upper ring 111 and a lower ring 113 attached to the upper surface 105A and the lower surface 105B of the substrate 105, respectively (e.g., via adhesives, not shown), in accordance with some embodiments.).
Regarding Claim 15, Liu-Zheng recites all the limitations of claim 13, as discussed above. Liu also discloses wherein the heat dissipation member is in contact with the first surface of the first substrate through the adhesive member and is in contact with the third surface of the second substrate (Fig. 1).
Regarding Claim 16, Liu-Zheng recites all the limitations of claim 1, as discussed above. Liu also discloses wherein the heat dissipation member is in contact with an area of the third surface, which overlaps with the first electronic component when viewed in the direction orthogonal to the fourth surface (Figs. 1 and 2).
Regarding Claim 17, Liu-Zheng recites all the limitations of claim 1, as discussed above. Liu also discloses wherein the at least one interposer is elongated along an edge of the first surface of the first substrate so as to at least partially surround the heat dissipation member (Fig. 1).
Regarding claim 18, Liu discloses an electronic device (Fig. 1) comprising:
a first substrate comprising a first surface and a second surface opposite to the first surface (Fig. 1, element 101 has a first and opposite second surface);
a second substrate comprising a third surface facing the first surface and a fourth surface opposite to the third surface (Fig. 1, element 105 has a first and opposite second surface 105A and B);
at least one interposer between the first surface and the third surface and electrically connecting the first substrate and the second substrate (Fig. 1 element S; and [0025] the system board 101 may be bonded to another substrate using external connections (not shown), which may be solder balls or other suitable conductive connections);
an electronic component on the second surface; and
a heat dissipation member (Fig. 1 element 220; and [0047] The double-sided heat dissipation module 200 also includes a second (or lower) heat spreader 220 located below the 3D-IC package module 103 (e.g., located on the side of the 3D-IC package module 103 near the second package components 109), as shown in FIG. 1. ) (Fig. 1 showing 220 is above 101, below 105, adjacent to S, and overlapping 107).
However, Liu does not explicitly disclose an electronic component on the second surface and which is in a solid phase at room temperature.
Zheng suggests an electronic component on the second surface (Fig. 8G, 80) and which is in a solid phase at room temperature (when selecting the filling material 70 and the thermal interface material layer 40 of the material combination, the melting point of the filling material 70 can be higher than the melting point of the thermal interface material layer 40, and the filling material 70 melting point higher than the reflow soldering of the welding point near the temperature, for example, filling material 70 is silica gel, The thermal interface material layer 40 is made of metal indium. when the substrate 10 is installed on the substrate 10 by means of FCBGA, it needs to use reflow soldering process, the temperature of the metal indium is heated to more than 200 ° C, the metal indium melting point is lower (generally about 156.61 ° C) to melt, but the melting point of the silica gel is high, will not melt, so as to, Although the metal indium is melted, it is still limited by the silica gel flow range, holding the good heat contact the chip 20 and the heat conducting cover 301. When the melting point of the filling material 70 is higher than the melting point of the thermal interface material layer 40, other materials can be combined, and the similar effect can be achieved).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu with the well-known silica gel material suggested by Zheng. The motivation would be to limit the flow of metal using the gel. Zheng at p. 11.
Regarding Claim 19, Liu-Zheng recites all the limitations of claims 2 and 18, as discussed above. Therefore, the rejections to claims 2 and 18 apply equally as well to claim 19.
Regarding Claim 20, Liu-Zheng recites all the limitations of claims 3 and 19, as discussed above. Therefore, the rejections to claims 3 and 19 apply equally as well to claim 20.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-Zheng, as discussed above, further in view of Nguyen (US PGPUB 20120187556 A1), [hereinafter Nguyen].
Regarding Claim 7, Liu-Zheng recites all the limitations of claim 1, as discussed above. Zheng also discloses wherein the heat dissipation member comprises: a phase change material having a melting point (The thermal interface material layer 40 is made of metal indium); and a matrix material configured to maintain the heat dissipation member in a gel phase at a temperature higher than the melting point of the phase change material (when selecting the filling material 70 and the thermal interface material layer 40 of the material combination, the melting point of the filling material 70 can be higher than the melting point of the thermal interface material layer 40, and the filling material 70 melting point higher than the reflow soldering of the welding point near the temperature, for example, filling material 70 is silica gel, The thermal interface material layer 40 is made of metal indium. when the substrate 10 is installed on the substrate 10 by means of FCBGA, it needs to use reflow soldering process, the temperature of the metal indium is heated to more than 200 ° C, the metal indium melting point is lower (generally about 156.61 ° C) to melt, but the melting point of the silica gel is high, will not melt, so as to, Although the metal indium is melted, it is still limited by the silica gel flow range, holding the good heat contact the chip 20 and the heat conducting cover 301. When the melting point of the filling material 70 is higher than the melting point of the thermal interface material layer 40, other materials can be combined, and the similar effect can be achieved).
However, Liu-Zheng do not explicitly disclose ranging from 40 degrees Celsius to 60 degrees Celsius.
Nguyen suggests ranging from 40 degrees Celsius to 60 degrees Celsius ([0020] In a further embodiment, an eutectic alloy of tin and bismuth powder (melting point 138 C), in a weight ratio of tin to bismuth of Sn:Bi::48:52 is used in combination with indium powder (melting point 158 C), in which the indium is present in a weight ratio of 1:1 with the formation of an In--Sn--Bi eutectic alloy having a melting point of 60 C. The polymer resin is crosslinked lightly to form a soft gel matrix within the In--Sn--Bi alloy.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu-Zheng with the gel material suggested by Nguyen. The motivation would be to achieve design specific flow of metal using the gel. Nguyen at [0020].
Regarding claim 8, Liu-Zheng-Nguyen suggest all the limitations of claim 7, as discussed above. Nguyen also suggests a tackifier configured to provide tack to the phase change material ([0008] The use of the epoxy resin derived from nut oil and/or of the epoxidized dimer fatty acid provides an optimum range of modulus for the thermal interface material. These epoxies perform two functions in the composition: they act as fluxing agents for the solder particles and they form a gel-like or tacky mass that physically keeps the solder particles connected. Both of these functions enable the formation of a solder alloy in situ and help it to remain in place within the thermal interface material, thus keeping the thermal impedance stable over time.)
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-Zheng-Nguyen, as discussed above, further in view of Choi (US PUB 12708031 B2), [hereinafter Choi].
Regarding Claim 9, Liu-Zheng-Nguyen recites all the limitations of claim 8, as discussed above. Zheng also suggests the matrix material comprises ([0008] The use of the epoxy resin).
However, Liu-Zheng-Nguyen do not explicitly disclose a thermoplastic organic material.
Choi suggests a thermoplastic organic material (1. A semiconductor package comprising: a printed circuit board including a connection portion; an IC chip arranged on the printed circuit board; a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion; a bonding layer arranged between the solder portion and the connection portion; and an underfill arranged between the IC chip and the printed circuit board, wherein the bonding layer includes thermosetting resin, wherein the underfill includes thermoplastic resin, wherein the bonding layer comprises printing epoxy on the printed circuit board in a form of a gel-type resin, ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu-Zheng-Nguyen with the gel material suggested by Choi. The motivation would be to achieve design specific flow of metal using the gel. Nguyen at [0020].
Regarding Claim 10, Liu-Zheng-Nguyen-Choi recites all the limitations of claim 9, as discussed above. Nguyen also suggests wherein the tackifier comprises at least one functional group different from a functional group of the matrix material (0008] The use of the epoxy resin derived from nut oil and/or of the epoxidized dimer fatty acid provides an optimum range of modulus for the thermal interface material. These epoxies perform two functions in the composition: they act as fluxing agents for the solder particles and they form a gel-like or tacky mass that physically keeps the solder particles connected. Both of these functions enable the formation of a solder alloy in situ and help it to remain in place within the thermal interface material, thus keeping the thermal impedance stable over time.)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-Zheng-Nguyen, as discussed above, further in view of YAMAZAKI (JP 2004253476 A using English translation), [hereinafter YAMAZAKI].
Regarding Claim 11, Liu-Zheng-Nguyen recites all the limitations of claim 8, as discussed above. Liu-Zheng-Nguyen do not explicitly recite wherein the tackifier has a glass transition temperature higher than the melting point of the phase change material.
Yamazaki suggests wherein the tackifier has a glass transition temperature higher than the melting point of the phase change material (YAMAZAKI [0028]: The glass transition temperature of the acrylic pressure-sensitive adhesive is usually 20 ° C. or lower, preferably about −70 to 0 ° C., and has tackiness at room temperature (23 ° C.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu-Zheng-Nguyen with the glass transition temperature suggested by Yamazaki. The motivation would be to achieve design specific flow of metal using the gel. Yamazaki at [0028].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-Zheng, as discussed above, further in view of Ge (WO 2023071671 A1 A using English translation), [hereinafter Ge].
Regarding Claim 14, Liu-Zheng recites all the limitations of claim 13, as discussed above. Liu-Zheng do not explicitly recite wherein the adhesive member comprises: a first adhesive layer on the first surface of the first substrate; and a second adhesive layer between the first adhesive layer and the heat dissipation member and comprising a hot melt adhesive
Ge suggests a first adhesive layer on the first surface of the first substrate; and a second adhesive layer between the first adhesive layer and the heat dissipation member and comprising a hot melt adhesive (In this embodiment, the material of the apron 410 is not limited, it can be the apron 410 made of double-sided adhesive, hot melt adhesive or epoxy resin bonding colloid, as long as the heat dissipation metal sheet 200 and the chip 100 can be connected and fixed. That is, it is ensured that the relative position of the heat dissipation metal sheet 200 and the chip 100 does not change, and the reliability of the chip module is improved. P. 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the thermal dissipation of Liu-Zheng with the hot melt adhesive suggested by Ge. The motivation would be to achieve design specific adhesion for reliability. Ge at p. 7.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Shen discloses an electronic device (Fig. 3) comprising:
a first substrate comprising a first surface and a second surface opposite to the first surface (Fig. 3, element 206 has a first and opposite second surface);
a second substrate comprising a third surface facing the first surface and a fourth surface opposite to the third surface (Fig. 3, element 203 has a first and opposite second surface);
at least one interposer between the first surface and the third surface and electrically connecting the first substrate and the second substrate (Fig. 11C, element 830 interposer);
a first electronic component on the fourth surface (The numerical symbol 8200 in FIG. 11B designates the lidded flip chip package integrated with a direct vapor chamber as shown in FIG. 11, wherein the flip chip 805 comprises of a plurality of chips as illustrated by the chips 820 and 821, as well other components, like one or more capacitors 822, that can also be placed on the substrate and covered by the molding material.); and
a heat dissipation member being in a solid phase at room temperature and in a space defined by the first substrate, the second substrate, and the at least one interposer so as to overlap with the first electronic component when viewed in a direction orthogonal to the fourth surface ([0027] FIG. 3A is schematic diagram for illustrating how the working liquid 209 as shown in FIG. 3 works to dissipate heat from the flip chip 205 to an ambient, in which the numerical symbol 2000A designates when the flip chip is generating heat, the working liquid 209 starts to work, wherein the dash arrows 209c and 209d illustrate that the heat generated by the flip chip 205 is dissipated from the flip chip 205 to the upper part 201 by the direct vapor chamber 200, and then to an ambient by a cooler, the solid arrows 209a designates that the working liquid 209 is at a liquid phase and flows back to the flip chip 205 along the layer of wick 202b based on a capillary action, and the dash wave arrows 209b designates that the working liquid 209 is at a vapor phase and flows to the upper part 201 along the channels 202a. It is noted that even though the two-phase heat dissipating structure 202 described in FIG. 3 and FIG. 3A comprises of a layer of wick 202b at a top surface of the lower part 203/204/205 and a plurality of channels 202a formed at a bottom surface of the base plate 201a, it can have other structures, like a lining of wick on the inner side of the closed chamber and a space inside the lining of wick, which will be described in another preferred embodiment of the present invention below; and Fig. 11C).
Huang 20230014476 suggests being in a solid phase at room temperature ([0050] In an embodiment, the heat dissipation material 23 has a high thermal conductivity, about 30-80 Watt/m-Kelvin (Wm.sup.−1K.sup.−1). For example, when an underfill (not shown) is formed between an active surface 25a of the electronic component 25 and the carrier structure 24 to insulate conductive bumps 250 from the outside, then the heat dissipation material 23 is solid indium, liquid metal or any other metal-containing material that is fluid at room temperature/high temperature to be used as a thermal interface material (TIM), such as a low-temperature melting thermally conductive material. If there is no underfill (not shown) between the active surface 25a of the electronic component 25 and the carrier structure 24, then liquid oil or other liquids without metal material can be used as a heat dissipation material.)
Humphries 20110186334 A1 Fig 1B discloses electronic circuits on both sides of a PCB.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALISON SLATER whose telephone number is (571)270-0375. The examiner can normally be reached MON-FRI 8AM-4PM EST, alt FRI.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALISON SLATER can be reached on 571-270-0375. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alison Slater/Supervisory Patent Examiner, Art Unit 2647
Prosecution Insights