DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2021/0109879) and Kuo (TW I715456).
Regarding claim 1, Das Sharma discloses a semiconductor system [FIG. 2, 7, 8B] comprising: a command address bus [FIG. 8C, 12, ¶0038, 0040, 0127: DDR4/DDRT, SML]; a data bus [FIG. 8A, 12: Mem Bus]; a management bus [FIG. 7, 8A, 12: Internal Routing, PCIe, GPIO Link]; a memory module including multiple memories and coupled to the command address bus, data bus and management bus [FIG. 7, 8C, ¶0085: memory module with DIMMs, buffers]; a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation [¶0083, 0098, 0099, 0125, 0126: a memory controller sending memory read/write transactions on a PCIe link based on address range check and the memory controller can determine from a particular address how the request is to be handled]; and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories [FIG. 7: CPU manages DIMMs and Buffers through GPIO Link].
Das Sharma does not explicitly discuss a baseboard management controller.
Kuo, however, discloses a baseboard management [Abstract: a baseboard management controller].
It would have been obvious to one of ordinary skill in the art to have a semiconductor system comprising a baseboard management controller in order to monitor and manage the overall status of the system (Abstract, Description).
Regarding claim 4, Das Sharma discloses the semiconductor system of claim 1, wherein each of the multiple memories includes a register configured to store therein a state information of the memory [¶0100: address map for a pooled memory system implemented as a set of registers].
Regarding claim 5, Das Sharma discloses the semiconductor system of claim 4, wherein each of the multiple memories is configured to transmit, to the baseboard management controller through the management bus, the state information stored in the register included therein [¶0119, 0123].
Regarding claim 12, Das Sharma discloses the semiconductor system of claim 1, wherein the management bus operates according to a scheme of memory module management control (M3C) interface [¶0118, 0122].
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2021/0109879) and Kuo (TW I715456) and GAO et al. (US 20250165346).
Regarding claim 2, Das Sharma discloses the semiconductor system of claim 1, but does not explicitly disclose wherein the baseboard management controller performs the management operation before the memory controller is powered up.
GAO et al., however, discloses the baseboard management controller performs the management operation before the memory controller is powered up [Claim 1: before in response to the server being powered on, starting the baseboard management controller from the flash memories storing the baseboard management controller firmware].
It would have been obvious to one of ordinary skill in the art to have the baseboard management controller performs the management operation before the memory controller is powered up in order to automatically recover the baseboard management firmware without disassembling of flash memories (¶0003).
Regarding claim 3, GAO et al. discloses the semiconductor system of claim 1, wherein the baseboard management controller performs the management operation in a situation in which the memory controller is unable to operate [Claim 1: before in response to the server being powered on, starting the baseboard management controller from the flash memories storing the baseboard management controller firmware].
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (US 2021/0109879) and Kuo (TW I715456) and GAO et al. (US 20250165346) and Ma et al. (US 12,688,085).
Regarding claim 6, Das Sharma discloses the semiconductor system of claim 5, but does not explicitly disclose wherein the state information includes one or more pieces of temperature information, error information and word line information.
Ma et al., however, discloses the state information includes one or more pieces of temperature information, error information and word line information [Col. 20: 20-26].
It would have been obvious to one of ordinary skill in the art to have the state information includes one or more pieces of temperature information, error information and word line information in order to provide a method for processing faulty memory module including acquiring first power down command used for instructing a baseboard management controller to perform power-down processing on a faulty memory module (Col. 1: 56-62).
Regarding claim 7, Ma et al. discloses the semiconductor system of claim 6, wherein the baseboard management controller performs the management operation by changing, when receiving the temperature information representing that a temperature of the memory is greater than a preset range, a level of a source voltage supplied to the memory [Col. 20: 20-26; Col. 22: 20-32].
Regarding claim 8, Ma et al. discloses the semiconductor system of claim 6, wherein the baseboard management controller performs the management operation by determining, based on the error information, whether an error rate of the memory is greater than a preset error rate [Col. 20: 20-26; Col. 22: 20-32].
Regarding claim 9, Ma et al. discloses the semiconductor system of claim 8, wherein the baseboard management controller performs the management operation by causing, when the error rate is determined as greater than the preset error rate, the memory to perform a repair operation on the memory [Col. 22: 20-32].
Regarding claim 10, Das Sharma discloses the semiconductor system of claim 6, wherein the word line information represents at least a word line accessed a preset number of times or more [¶0096].
Regarding claim 11, Das Sharma discloses the semiconductor system of claim 10, wherein the baseboard management controller performs the management operation by causing, according to the word line information, the memory to perform a refresh operation for neighboring word lines adjacent to the word line [¶0158].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ma et al. (US 12,688,085) discloses after a first power-down command is acquired, then baseboard management controller of the memory resource pool may send state acquisition command to the baseboard management controller of the host server corresponding to the target memory module.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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