DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 19/010,178 on January 6, 2025. Claims 1-19 are pending.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on January 6, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
4. Claims 13-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 recites limitations of the various modules, first and second scan line, first and second voltage lines, etc. This level of detail, including connections, in its entirety, is not taught by the prior art. Claims 14-17 depend from Claim 13.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-4, 11 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon et al. ( US 2020/0126485 A1 ).
Moon teaches in Claim 1:
A thin-film transistor, applied to a pixel circuit ( Figure 3, [0060] discloses a driving transistor TD in a pixel circuit PC ), and comprising:
a first gate, configured to be applied with a data voltage ( Figure 3, [0060] discloses a first gate electrode GE11 which receives a data voltage Vdata );
a second gate, located on two opposite sides of an active layer of the thin-film transistor with the first gate ( Figure 3, [0060] discloses a second gate electrode GE12 which receives an independent bias voltage Vb ), and configured to: use at least two different voltages within different preset grayscale intervals, and use the same voltage within the same preset grayscale interval. ( Figure 6, [0050]-[0051] disclose a variety of voltage values for Vb, along with multiple driving voltage ranges, such as a first and second driving voltage range. As for intervals, please note each entry row in Figure 6 is interpreted as an interval. For example, for Vb = -1, Vb = 0 and Vb = 1 are interpreted as different preset grayscale intervals and as shown, each interval has its own voltage parameters. For the first two interpreted intervals, there are two different voltage parameters and for the third interpreted interval, there is its own voltage parameter. Furthermore, [0081]+ disclose multiple conditions, at least four )
Moon teaches in Claim 2:
The thin-film transistor according to claim 1, wherein the preset grayscale intervals comprise a first preset grayscale interval, a second preset grayscale interval, and a third preset grayscale interval, one grayscale within the first preset grayscale interval is less than one grayscale within the second preset grayscale interval, and one grayscale within the second preset grayscale interval is less than one grayscale within the third preset grayscale interval; and a voltage applied to the second gate within the third preset grayscale interval is at least different from a voltage applied to the second gate within the first preset grayscale interval. ( To expand on the reasoning of Claim 1, please note Figure 6 which shows at least three entries, for Vb = -1, Vb = 0 and Vb = 1. As the driving voltage range VD_range decreases, the grayscale levels also decrease. As such, Vb = -1 is read as a first preset grayscale which is “less than” the grayscale level associated with Vb = 0 (read as a second preset grayscale), which in turn is “less than” the grayscale associated with Vb = 1 (read as a third preset grayscale). As noted above, each of these entries has a different Vb and driving voltage range value )
Moon teaches in Claim 3:
The thin-film transistor according to claim 2, wherein within the first preset grayscale interval, a voltage applied to the second gate is a first voltage ( Figure 6 shows that for Vb = -1 that there is this voltage associated with the VD_range );
within the second preset grayscale interval, the voltage applied to the second gate is a second voltage ( Figure 6 shows that for Vb = 0 that there is this voltage associated with the VD_range ); and
within the third preset grayscale interval, the voltage applied to the second gate is a third voltage ( Figure 6 shows that for Vb = 1 that there is this voltage associated with the VD_range ), wherein a direction of the first voltage is opposite to a direction of the data voltage, and a direction of the second voltage and a direction of the third voltage are both the same as the direction of the data voltage. ( Figure 6 shows the interpreted first voltage being negative and opposite to Vdata, as detailed in [0066], whereas the interpreted second and third voltage are both the same direction as Vdata )
Moon teaches in Claim 4:
The thin-film transistor according to claim 3, wherein the first voltage is an adjustable voltage, and the second voltage and the third voltage are both fixed voltages. ( [0056] discloses being able to gently adjust the VD_range and Vb and [0075] discloses controlling and adjusting other values shown in Figure 6 based on Vb. Respectfully, the values shown are fixed, but Moon clearly teaches of being able to adjust if needed )
Moon teaches in Claim 11:
A pixel circuit, comprising a driving module, a first voltage writing module, a second voltage writing module, and a light emitting module ( Figure 3, [0059]+ disclose a driving transistor TD (read as a driving module), a switching transistor TS (read as a first voltage writing module), Vb/VL2 aspects (read as a second voltage writing module) and an OLED (read as a light emitting module) ), wherein the driving module comprises the thin-film transistor according to claim 1 ( Figure 3 shows driving TFT TD ); the first voltage writing module is connected to the thin-film transistor, and is configured to transmit the data voltage to the thin-film transistor to write the data voltage to a first gate of the thin-film transistor ( Figure 3 shows transistor TS transmits Vdata to the TD ); the second voltage writing module is connected to a second gate of the thin-film transistor, and is configured to transmit at least two different voltages to the second gate of the thin-film transistor within different preset grayscale intervals in a time division manner ( Figure 3 shows Vb/VL2 connected to the second gate electrode GE12 of TD. Figure 6 shows the various levels of Vb and Figure 5 shows the time division based on the grayscale and other voltages ); and the thin-film transistor and the light emitting module are connected in series between a first power line and a second power line ( Figure 3 shows TD and OLED in series between ELVDD and ELVSS ), and the thin-film transistor is configured to drive the light emitting module to emit light during a light emitting stage. ( Figure 3, [0066] discloses details of driving the OLED )
Moon teaches in Claim 18:
A driving method for a pixel circuit, wherein the pixel circuit comprises a driving module, a first voltage writing module, a second voltage writing module, and a light emitting module ( Figure 3, [0059]+ disclose a driving transistor TD (read as a driving module), a switching transistor TS (read as a first voltage writing module), Vb/VL2 aspects (read as a second voltage writing module) and an OLED (read as a light emitting module) ), wherein the driving module comprises the thin-film transistor according to claim 1 ( Figure 3 shows driving TFT TD ); and the driving method for a pixel circuit comprises: during a data writing and compensation stage ( [0088] discloses compensation algorithms ), controlling the first voltage writing module to transmit the data voltage to the thin-film transistor ( Figure 3 shows transistor TS transmits Vdata to the TD ), to write the data voltage to the first gate, while controlling the second voltage writing module to transmit at least two different voltages to a second gate of the thin-film transistor within different preset grayscale intervals in a time division manner ( Figure 3 shows Vb/VL2 connected to the second gate electrode GE12 of TD. Figure 6 shows the various levels of Vb and Figure 5 shows the time division based on the grayscale and other voltages ); and during a light emitting stage, controlling the thin-film transistor to drive the light emitting module to emit light. ( Figure 3, [0066] discloses details of driving the OLED )
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. ( US 2020/0126485 A1 ).
As per Claim 5:
Moon may not explicitly teach “wherein a ratio of the first voltage to the data voltage ranges from −2 to −0.2.”
However, Moon teaches in [0066] of Vdata being applied to the first gate electrode GE11 and Vb is applied to the second gate electrode GE12. It is clear the same transistor with two gates will have a ratio relationship between the voltages applied to the two gates. Figure 5 shows relationships between the values and Figure 6 further shows the various values which change (in ratio) to Vb. Respectfully, one of ordinary skill in the art would realize the ratio of these two voltages would be designed to be optimize the ratios of voltages to the driving transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the ratio of the voltages to the driving transistor, with the motivation that it is an optimization issue to do so. Please see Figures 5 and 6 for the relationship between these voltages.
Moon teaches in Claim 6:
The thin-film transistor according to claim 5, wherein the second voltage is reused as the third voltage, and an absolute value of the second voltage ranges from 0 V to 7 V. ( Figure 6 shows the range of voltages within the claimed range. Please note the Vb values )
Moon teaches in Claim 7:
The thin-film transistor according to claim 6, wherein the thin-film transistor according to claim 3, wherein the first voltage is an adjustable voltage, and the second voltage and the third voltage are both adjustable voltages. ( [0056] discloses being able to gently adjust the VD_range and Vb and [0075] discloses controlling and adjusting other values shown in Figure 6 based on Vb. Respectfully, the values shown are fixed, but Moon clearly teaches of being able to adjust if needed )
As per Claim 8:
Moon does not explicitly teach “wherein a ratio of the first voltage to the data voltage ranges from −2 to −0.2.”
However, Moon teaches in [0066] of Vdata being applied to the first gate electrode GE11 and Vb is applied to the second gate electrode GE12. It is clear the same transistor with two gates will have a ratio relationship between the voltages applied to the two gates. Figure 5 shows relationships between the values and Figure 6 further shows the various values which change (in ratio) to Vb. Respectfully, one of ordinary skill in the art would realize the ratio of these two voltages would be designed to be optimize the ratios of voltages to the driving transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the ratio of the voltages to the driving transistor, with the motivation that it is an optimization issue to do so. Please see Figures 5 and 6 for the relationship between these voltages.
As per Claim 9:
Moon does not explicitly teach “wherein the second voltage is reused as the third voltage, and a ratio of the second voltage to the data voltage ranges from 0.2 to 2.”
However, Moon teaches in [0066] of Vdata being applied to the first gate electrode GE11 and Vb is applied to the second gate electrode GE12. It is clear the same transistor with two gates will have a ratio relationship between the voltages applied to the two gates. Figure 5 shows relationships between the values and Figure 6 further shows the various values which change (in ratio) to Vb. Respectfully, one of ordinary skill in the art would realize the ratio of these two voltages would be designed to be optimize the ratios of voltages to the driving transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the ratio of the voltages to the driving transistor, with the motivation that it is an optimization issue to do so. Please see Figures 5 and 6 for the relationship between these voltages.
As per Claim 10:
Moon does not explicitly teach “wherein the first voltage is an adjustable voltage, the second voltage is a fixed voltage, and the third voltage is an adjustable voltage; a ratio of the first voltage to the data voltage ranges from −2 to −0.2.”
However, Moon teaches in [0066] of Vdata being applied to the first gate electrode GE11 and Vb is applied to the second gate electrode GE12. It is clear the same transistor with two gates will have a ratio relationship between the voltages applied to the two gates. Figure 5 shows relationships between the values and Figure 6 further shows the various values which change (in ratio) to Vb. Respectfully, one of ordinary skill in the art would realize the ratio of these two voltages would be designed to be optimize the ratios of voltages to the driving transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the ratio of the voltages to the driving transistor, with the motivation that it is an optimization issue to do so. Please see Figures 5 and 6 for the relationship between these voltages.
10. Claims 12 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Moon et al.
( US 2020/0126485 A1 ), as applied to Claim 11, further in view of Zhu et al.
( US 2018/0190194 A1 ).
As per Claim 12:
Moon does not explicitly teach “wherein a control terminal of the first voltage writing module is connected to a first scan line, and a control terminal of the second voltage writing module is connected to the first scan line.”
However, in the same field of endeavor, pixel circuits with a second gate for the driving transistor, Zhu teaches of a driving transistor DT1 with a double gate structure, ( Zhu, Figure 3, [0027] ). Notably, the transistor T3 applies a voltage to the second gate of DT1, similar to Moon. Notably, this transistor is controlled by Scan1, the same Scan1 also applied to the gate of transistor T2. Respectfully, this is a well known structure.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the scan signal layout, as taught by Zhu, with the motivation that by using the scan signal, the stage timings of Figures 9 and 10 can be carried, resulting in proper threshold detection of the drive transistor, ( Zhu, Figures 9 and 10, [0069] ).
As per Claim 19:
Moon does not explicitly teach “wherein the pixel circuit further comprises a compensation module, an initialization module, a first light emission control module, and a second light emission control module; the driving method for a pixel circuit further comprises: during an initialization stage, controlling the initialization module to transmit an initialization voltage on an initialization signal line to a first terminal of the light emitting module, and controlling the first light emission control module to transmit a voltage on a first power line to the first gate through the compensation module; and during the data writing and compensation stage, controlling the first voltage writing module to transmit the data voltage to the thin-film transistor, to write the data voltage to the first gate, while controlling the second voltage writing module to transmit at least two different voltages to a second gate of the thin-film transistor within different preset grayscale intervals in a time division manner comprises: during the data writing and compensation stage, controlling the first gate to discharge through the compensation module, the thin-film transistor, and the first voltage writing module, in order to write a voltage containing information about the data voltage and threshold voltage information to the first gate; while controlling the second voltage writing module to transmit at least two different voltages to the second gate of the thin-film transistor within different preset grayscale intervals in a time division manner.”
However, in the same field of endeavor, pixel circuits with a second gate for the driving transistor, Zhu teaches of a driving transistor DT1 with a double gate structure, ( Zhu, Figure 3, [0027] ). Notably, the transistor T3 applies a voltage to the second gate of DT1, similar to Moon. Notably, this transistor is controlled by Scan1, the same Scan1 also applied to the gate of transistor T2. Respectfully, this is a well known structure. To emphasize:
“wherein the pixel circuit further comprises a compensation module, an initialization module, a first light emission control module ( Zhu, Figure 6, [0036] discloses transistors T3 for compensation and T4 for initialization and T1 for light emission ), and a second light emission control module ( Respectfully, two emission control transistors, on opposite sides of the driving transistor is well known and Examiner asserts Official Notice to this ); the driving method for a pixel circuit further comprises: during an initialization stage, controlling the initialization module to transmit an initialization voltage on an initialization signal line to a first terminal of the light emitting module, and controlling the first light emission control module to transmit a voltage on a first power line to the first gate through the compensation module; and during the data writing and compensation stage, controlling the first voltage writing module to transmit the data voltage to the thin-film transistor, to write the data voltage to the first gate, ( Figures 9 and 10, [0069] disclose the initialization stage P1, threshold detection stage P2 and light-emission stage P4 ) while controlling the second voltage writing module to transmit at least two different voltages to a second gate of the thin-film transistor within different preset grayscale intervals in a time division manner comprises:
during the data writing and compensation stage, controlling the first gate to discharge through the compensation module, the thin-film transistor, and the first voltage writing module, in order to write a voltage containing information about the data voltage and threshold voltage information to the first gate; while controlling the second voltage writing module to transmit at least two different voltages to the second gate of the thin-film transistor within different preset grayscale intervals in a time division manner ( The same reasoning of Claim 1 is applicable here as well: Figure 6, [0050]-[0051] disclose a variety of voltage values for Vb, along with multiple driving voltage ranges, such as a first and second driving voltage range. As for intervals, please note each entry row in Figure 6 is interpreted as an interval. For example, for Vb = -1, Vb = 0 and Vb = 1 are interpreted as different preset grayscale intervals and as shown, each interval has its own voltage parameters. For the first two interpreted intervals, there are two different voltage parameters and for the third interpreted interval, there is its own voltage parameter. Furthermore, [0081]+ disclose multiple conditions, at least four )”
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621