Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 01/06/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 8 is objected to because of the following informalities:
Regarding claim 8, in line 3, “a processing circuitry” appears that it should read as “processing circuitry”, because the term “circuitry” is a non-count noun for which the indefinite article “a” is grammatically improper. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 5, 11, 12, 18, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4, the recitation “a primary phase” renders the claim indefinite because it is unclear whether “a primary phase” is one of “the at least one phase” previously recited in claim 1 or is a separate phase not previously recited, such that the metes and bounds of the claim cannot be determined. For purposes of examination, “a primary phase” is interpreted as a phase operated by the second controller. Dependent claim 5 of claim 4 inherits the deficiencies of claim 4 and is therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Regarding claim 11, the recitation “a primary phase” renders the claim indefinite for the same reasons set forth above with respect to claim 4, it being unclear whether “a primary phase” is one of “the at least one phase” previously recited in claim 8 or a separate phase not previously recited. Dependent claim 12 of claim 11 inherits the deficiencies of claim 11 and is therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Regarding claim 18, the recitation “a primary phase” renders the claim indefinite for the same reasons set forth above with respect to claim 4, it being unclear whether “a primary phase” is one of “the at least one phase” previously recited in claim 15 or a separate phase not previously recited. Dependent claims 19 and 20 of claim 18 inherit the deficiencies of claim 18 and are therefore also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6, 7, 8, 9, 13, 14, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Barus et al. (US Patent Application Publication US 2013/0329474 A1, hereinafter “Barus”) in view of Douglas et al. (US Patent Application Publication US 2007/0174601 A1, hereinafter “Douglas”) and Samii et al. (US Patent Application Publication US 2017/0277607 A1, hereinafter “Samii”).
Regarding claim 1, Barus discloses (see Fig. 1 and Fig. 2) a computer-implemented method (see [0009] of Barus “systems, methods, techniques, instruction sequences and computer program products”) comprising: detecting, by a control switch (the power management processor of the power supply 103, shown as the power supply 203 in Fig. 2, operating in cooperation with the microprocessor 101 and the multiplexing logic device 105; see [0012] of Barus “power supplies 103 and 107 include a power management processor”), a failure of a first controller (phase controller 111, shown as the phase controller 211 in Fig. 2) of a first circuit (the input and control path comprising the power supply 103, the multiplexing logic device 105, the phase controller 111 and the phase regulator 115, shown in Fig. 2 as the power supply 203, the multiplexing logic device 205, the phase controller 211 and the phase regulator 215; see [0014] of Barus “a redundant communication path from the power supply 103” and see [0014] of Barus “to each of the N+2 phase controllers”), the first circuit controlling power output from at least one phase (the phase regulator 115 of that path delivers the output current of one phase of the multi-phase power converter to the electrical load; see [0010] of Barus “a phase controller controls each phase of the multi-phase power converter”) (see [0021] of Barus “the power supplies 203 and 207 detect failure of the phase controller 211”); and receiving, from the second controller (phase controller 113, shown as the phase controller 213 in Fig. 2), a control signal having commands for operating the at least one phase (the phase regulator 117 of the second circuit receives from the phase controller 113 the control signals that set the output current of that phase, the phase controller 113 being one of the remaining phase controllers that increase the delivered output current upon the failure of the phase controller 111) (see [0015] of Barus “The phase controller 111 generates control signals to control the current at the output of the phase regulator 115” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Barus does not disclose a second controller of a second circuit to retrieve an image for operating the at least one phase; and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image.
However, Douglas teaches (see Fig. 2 and Fig. 3) a second controller (secondary controller 106) of a second circuit (the redundant control path comprising the secondary controller 106, its input/output interface 112 and its memory device 118) to retrieve an image for operating the at least one phase (the secondary controller 106 retrieves from its memory device 118 the copy of the firmware image, which comprises the operating system 122 that the controller processor 124 executes to manage the subordinate devices 114); and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image (the subordinate devices 114 receive from the secondary controller 106 the management commands that the secondary controller 106 issues by executing the retrieved firmware image) (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller” and see [0037] of Douglas “its role may be assumed by the secondary controller 106”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus to include a second controller of a second circuit to retrieve an image for operating the at least one phase, and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image, as taught by Douglas, because Barus already requires the surviving phase controller to carry the failed controller’s share of the phase output from the same control values, its phase controllers being operated in active redundancy (see [0015] of Barus “the redundant path power subsystem 100 implements active redundancy”) and the survivors receiving the control values of the controller that failed (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which one controller’s operating image is placed on a redundant peer controller, so that applying that mechanism in Barus predictably supplies the second controller with the operating configuration that Barus already requires it to have when it assumes the at least one phase.
Barus does not disclose initiating, by the control switch, a second controller.
However, Samii teaches (see Fig. 7) initiating, by the control switch (the master controller of the centralized approach), a second controller (the controller that the master controller determines should reconfigure to primary status and notifies to reconfigure) (see [0045] of Samii “a master controller detects failures of all other controllers in the system, and determines which controller should reconfigure to primary status” and see [0045] of Samii “the master controller notifies the respective controller to reconfigure”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas to include initiating, by the control switch, a second controller, as taught by Samii, because it can provide a coordinated and deterministic failover in which the same entity that detected the failure designates and directs the particular backup that is to assume control, thereby avoiding contention among the remaining controllers and increasing the reliability of the power system.
Regarding claim 2, Barus discloses (see Fig. 1 and Fig. 2) wherein the control switch is configured to operate the at least one phase to output power in accordance with the commands (the control switch operates the phase regulators to deliver output current in accordance with the control signals) (see [0011] of Barus “Each phase regulator in the array is coupled with a phase controller (e.g., voltage regulator module (VRM) controller) to receive control signals” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Regarding claim 6, Barus does not disclose wherein the first controller comprises an original image for operating the at least one phase.
However, Douglas teaches (see Fig. 2 and Fig. 3) wherein the first controller (primary controller 104) comprises an original image for operating the at least one phase (the primary controller stores a firmware image written by the management module) (see [0017] of Douglas “a firmware image written by a management module to a first memory device of the primary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas and Samii wherein the first controller comprises an original image for operating the at least one phase, as taught by Douglas, because Barus already requires each phase controller to operate its phase from control values held at that controller (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism in which the controller to be duplicated holds an original image in its own memory device 118, so that providing the first controller of Barus with such an original image predictably makes that configuration available in a form that can be copied to the second controller.
Regarding claim 7, Barus does not disclose wherein the second controller comprises the image as a copy of an original image of the first controller.
However, Douglas teaches (see Fig. 2 and Fig. 4) wherein the second controller (secondary controller 106) comprises the image as a copy of an original image of the first controller (the secondary controller stores a copy of the primary controller’s firmware image) (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas and Samii wherein the second controller comprises the image as a copy of an original image of the first controller, as taught by Douglas, because Barus already requires the surviving phase controller to operate the failed controller’s phase from the same control values (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which a copy of the original image is held on the redundant peer, so that placing such a copy on the second controller of Barus predictably yields a controller that operates the at least one phase in the same manner as the failed first controller.
Regarding claim 8, Barus discloses (see Fig. 1, Fig. 2, and Fig. 4) a control switch (the power management processor of the power supply 103, shown as the power supply 203 in Fig. 2, operating in cooperation with the microprocessor 101 and the multiplexing logic device 105; see [0012] of Barus “power supplies 103 and 107 include a power management processor”) comprising: a memory comprising computer readable instructions (memory 403 of Fig. 4, which stores the computer readable program code by which the described operations are carried out, the redundant path power subsystem 100 of Fig. 1 being the redundant path power subsystem 415 of Fig. 4; see [0037] of Barus “The redundant path power subsystem 415 is embodied in motherboard of the computer system”) (see [0029] of Barus “a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon”); and a processing circuitry (the power management processor of the power supply 103, together with the microprocessor 101 shown as the microprocessor unit 401 in Fig. 4) for executing the computer readable instructions, the computer readable instructions controlling the processing circuitry to perform operations comprising: detecting a failure of a first controller (phase controller 111, shown as the phase controller 211 in Fig. 2) of a first circuit (the input and control path comprising the power supply 103, the multiplexing logic device 105, the phase controller 111 and the phase regulator 115, shown in Fig. 2 as the power supply 203, the multiplexing logic device 205, the phase controller 211 and the phase regulator 215; see [0014] of Barus “a redundant communication path from the power supply 103” and see [0014] of Barus “to each of the N+2 phase controllers”), the first circuit controlling power output from at least one phase (the phase regulator 115 of that path delivers the output current of one phase of the multi-phase power converter to the electrical load; see [0010] of Barus “a phase controller controls each phase of the multi-phase power converter”) (see [0021] of Barus “the power supplies 203 and 207 detect failure of the phase controller 211”); and receiving, from the second controller (phase controller 113, shown as the phase controller 213 in Fig. 2), a control signal having commands for operating the at least one phase (the phase regulator 117 of the second circuit receives from the phase controller 113 the control signals that set the output current of that phase, the phase controller 113 being one of the remaining phase controllers that increase the delivered output current upon the failure of the phase controller 111) (see [0015] of Barus “The phase controller 111 generates control signals to control the current at the output of the phase regulator 115” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Barus does not disclose a second controller of a second circuit to retrieve an image for operating the at least one phase; and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image.
However, Douglas teaches (see Fig. 2 and Fig. 3) a second controller (secondary controller 106) of a second circuit (the redundant control path comprising the secondary controller 106, its input/output interface 112 and its memory device 118) to retrieve an image for operating the at least one phase (the secondary controller 106 retrieves from its memory device 118 the copy of the firmware image, which comprises the operating system 122 that the controller processor 124 executes to manage the subordinate devices 114); and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image (the subordinate devices 114 receive from the secondary controller 106 the management commands that the secondary controller 106 issues by executing the retrieved firmware image) (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller” and see [0037] of Douglas “its role may be assumed by the secondary controller 106”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus to include a second controller of a second circuit to retrieve an image for operating the at least one phase, and receiving, from the second controller, a control signal having commands for operating the at least one phase based on the image, as taught by Douglas, because Barus already requires the surviving phase controller to carry the failed controller’s share of the phase output from the same control values, its phase controllers being operated in active redundancy (see [0015] of Barus “the redundant path power subsystem 100 implements active redundancy”) and the survivors receiving the control values of the controller that failed (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which one controller’s operating image is placed on a redundant peer controller, so that applying that mechanism in Barus predictably supplies the second controller with the operating configuration that Barus already requires it to have when it assumes the at least one phase.
Barus does not disclose initiating a second controller.
However, Samii teaches (see Fig. 7) initiating a second controller (the controller that the master controller determines should reconfigure to primary status and notifies to reconfigure) (see [0045] of Samii “a master controller detects failures of all other controllers in the system, and determines which controller should reconfigure to primary status” and see [0045] of Samii “the master controller notifies the respective controller to reconfigure”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas to include initiating a second controller, as taught by Samii, because it can provide a coordinated and deterministic failover in which the same entity that detected the failure designates and directs the particular backup that is to assume control, thereby avoiding contention among the remaining controllers and increasing the reliability of the power system.
Regarding claim 9, Barus discloses (see Fig. 1 and Fig. 2) wherein the processing circuitry is configured to operate the at least one phase to output power in accordance with the commands (the microprocessor operates the phase regulators to deliver output current in accordance with the control signals) (see [0011] of Barus “Each phase regulator in the array is coupled with a phase controller (e.g., voltage regulator module (VRM) controller) to receive control signals” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Regarding claim 13, Barus does not disclose wherein the first controller comprises an original image for operating the at least one phase.
However, Douglas teaches (see Fig. 2 and Fig. 3) wherein the first controller (primary controller 104) comprises an original image for operating the at least one phase (see [0017] of Douglas “a firmware image written by a management module to a first memory device of the primary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas and Samii wherein the first controller comprises an original image for operating the at least one phase, as taught by Douglas, because Barus already requires each phase controller to operate its phase from control values held at that controller (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism in which the controller to be duplicated holds an original image in its own memory device 118, so that providing the first controller of Barus with such an original image predictably makes that configuration available in a form that can be copied to the second controller.
Regarding claim 14, Barus does not disclose wherein the second controller comprises the image as a copy of an original image of the first controller.
However, Douglas teaches (see Fig. 2 and Fig. 4) wherein the second controller (secondary controller 106) comprises the image as a copy of an original image of the first controller (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas and Samii wherein the second controller comprises the image as a copy of an original image of the first controller, as taught by Douglas, because Barus already requires the surviving phase controller to operate the failed controller’s phase from the same control values (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which a copy of the original image is held on the redundant peer, so that placing such a copy on the second controller of Barus predictably yields a controller that operates the at least one phase in the same manner as the failed first controller.
Regarding claim 15, Barus discloses (see Fig. 1 and Fig. 2) a system (redundant path power subsystem 100, shown as the redundant path power subsystem 200 in Fig. 2) comprising: a first circuit (the input and control path comprising the power supply 103, the multiplexing logic device 105, the phase controller 111 and the phase regulator 115, shown in Fig. 2 as the power supply 203, the multiplexing logic device 205, the phase controller 211 and the phase regulator 215; see [0014] of Barus “a redundant communication path from the power supply 103” and see [0014] of Barus “to each of the N+2 phase controllers”) comprising a control switch (the power management processor of the power supply 103, shown as the power supply 203 in Fig. 2, operating in cooperation with the microprocessor 101 and the multiplexing logic device 105; see [0012] of Barus “power supplies 103 and 107 include a power management processor”) and a first controller (phase controller 111, shown as the phase controller 211 in Fig. 2); and a plurality of circuits (the plurality of input and control paths of the redundant path power subsystem 100, one such path for each of the N+2 phase controllers and its phase regulator), the first circuit being included in the plurality of circuits (see [0011] of Barus “illustrate three of the N+2 phase controllers in the redundant path power subsystem 100”); wherein the control switch is configured to: detect a failure of the first controller of the first circuit, the first circuit controlling power output from at least one phase (the phase regulator 115 of that path delivers the output current of one phase of the multi-phase power converter to the electrical load; see [0010] of Barus “a phase controller controls each phase of the multi-phase power converter”) (see [0021] of Barus “the power supplies 203 and 207 detect failure of the phase controller 211”); and receive, from the second controller (phase controller 113, shown as the phase controller 213 in Fig. 2) of a second circuit (the input and control path comprising the phase controller 113 and the phase regulator 117, shown in Fig. 2 as the phase controller 213 and the phase regulator 217) of the plurality of circuits, a control signal having commands for operating the at least one phase (the phase regulator 117 of the second circuit receives from the phase controller 113 the control signals that set the output current of that phase, the phase controller 113 being one of the remaining phase controllers that increase the delivered output current upon the failure of the phase controller 111) (see [0015] of Barus “The phase controller 111 generates control signals to control the current at the output of the phase regulator 115” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Barus does not disclose a second controller of a second circuit of the plurality of circuits to retrieve an image for operating the at least one phase; and receive, from the second controller, a control signal having commands for operating the at least one phase based on the image.
However, Douglas teaches (see Fig. 2 and Fig. 3) a second controller (secondary controller 106) of a second circuit (the redundant control path comprising the secondary controller 106, its input/output interface 112 and its memory device 118) to retrieve an image for operating the at least one phase (the secondary controller 106 retrieves from its memory device 118 the copy of the firmware image, which comprises the operating system 122 that the controller processor 124 executes to manage the subordinate devices 114); and receive, from the second controller, a control signal having commands for operating the at least one phase based on the image (the subordinate devices 114 receive from the secondary controller 106 the management commands that the secondary controller 106 issues by executing the retrieved firmware image) (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller” and see [0037] of Douglas “its role may be assumed by the secondary controller 106”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus to include a second controller of a second circuit of the plurality of circuits to retrieve an image for operating the at least one phase, and receive, from the second controller, a control signal having commands for operating the at least one phase based on the image, as taught by Douglas, because Barus already requires the surviving phase controller to carry the failed controller’s share of the phase output from the same control values, its phase controllers being operated in active redundancy (see [0015] of Barus “the redundant path power subsystem 100 implements active redundancy”) and the survivors receiving the control values of the controller that failed (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which one controller’s operating image is placed on a redundant peer controller, so that applying that mechanism in Barus predictably supplies the second controller with the operating configuration that Barus already requires it to have when it assumes the at least one phase.
Barus does not disclose wherein the control switch is configured to initiate a second controller.
However, Samii teaches (see Fig. 7) wherein the control switch (the master controller of the centralized approach) is configured to initiate a second controller (the controller that the master controller determines should reconfigure to primary status and notifies to reconfigure) (see [0045] of Samii “a master controller detects failures of all other controllers in the system, and determines which controller should reconfigure to primary status” and see [0045] of Samii “the master controller notifies the respective controller to reconfigure”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas wherein the control switch is configured to initiate a second controller, as taught by Samii, because it can provide a coordinated and deterministic failover in which the same entity that detected the failure designates and directs the particular backup that is to assume control, thereby avoiding contention among the remaining controllers and increasing the reliability of the power system.
Regarding claim 16, Barus discloses (see Fig. 1 and Fig. 2) wherein the control switch is configured to operate the at least one phase to output power in accordance with the commands (the control switch operates the phase regulators to deliver output current in accordance with the control signals) (see [0011] of Barus “Each phase regulator in the array is coupled with a phase controller (e.g., voltage regulator module (VRM) controller) to receive control signals” and see [0022] of Barus “the remaining N+1 phase controllers increase the output current delivered by N+1 phase regulators”).
Claims 3, 4, 5, 10, 11, 12, 17, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Barus in view of Douglas, Samii, and the ISL68137 datasheet (“ISL68137 Digital Dual Output, 7-Phase Configurable PWM Controller with Adaptive Voltage Scaling Bus (AVSBus),” Datasheet FN8757 Rev. 1.00, Intersil Americas LLC (Renesas Electronics Corporation), Jun. 26, 2017, hereinafter “ISL68137”).
Regarding claim 3, Barus does not disclose wherein the second controller comprises a first loop and a second loop.
However, ISL68137 teaches (see Fig. 1) wherein the second controller (the ISL68137 digital dual output PWM controller) comprises a first loop (the Output 0 regulation loop of Fig. 1, comprising the VSEN0/RGND0 remote voltage sense inputs, VSA ADC, VDROOP, PID compensator and DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-0) and a second loop (the Output 1 regulation loop of Fig. 1, comprising the VSEN1/RGND1 remote voltage sense inputs, a second VSA ADC, VDROOP, PID compensator and a second DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-1), the two loops being arbitrated by the LOOP MANAGER of Fig. 1 (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “digital dual output, flexible multiphase (X+Y ≤ 7) PWM controller”; see p. 13 of ISL68137 “The ISL68137 supports up to two regulated outputs through seven configurable phases”; and see p. 17 of ISL68137 “the regulation loop is entirely digital”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas and Samii wherein the second controller comprises a first loop and a second loop, as taught by ISL68137, because it can permit a single controller to independently regulate two separate output rails, thereby providing a second, independently configurable regulation loop within the same controller and reducing the number of controllers required in the multiphase power subsystem of Barus.
Regarding claim 4, as best understood, Barus does not disclose wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop.
However, ISL68137 teaches (see Fig. 1 and Fig. 2) wherein the second controller (the ISL68137 digital dual output PWM controller) is configured to utilize a first loop (the Output 0 regulation loop of Fig. 1) to operate a primary phase (the phase driven by output PWM0 and sensed at CS0/CSRTN0, assigned to Output 0; Fig. 2 shows six such phases assigned to VOUT0) and a second loop (the Output 1 regulation loop of Fig. 1, which regulates VOUT1 and to which phases are separately assigned; Fig. 2 shows the phase driven by output PWM6 assigned to VOUT1) (see p. 6, Fig. 2 of ISL68137; see p. 13 of ISL68137 “Either output is capable of controlling up to seven phases in any arbitrary mix”; and see p. 13 of ISL68137 “For Output 0, phases would be assigned starting from Phase 0”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas and Samii wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop, as taught by ISL68137, because it can permit the phase already assigned to the second controller to remain regulated by the first loop while leaving the second loop separately configurable, thereby providing an independent regulation path within the second controller without adding a further controller to the power subsystem of Barus.
Barus does not disclose wherein the second loop serves as a backup to the first controller.
However, Samii teaches (see Fig. 3) a control entity that serves as a backup to the first controller (second controller 14, which operates in a hot standby status mode and is reconfigured to primary status upon a failure of the first controller 12) (see [0030] of Samii “the second controller 14 will be reconfigured as the primary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop serves as a backup to the first controller, as taught by Samii, because the second loop is an independent regulation path that is not committed to the primary phase, and assigning to it the hot standby backup role of Samii permits the second controller to assume the at least one phase of the failed first controller without interrupting regulation of the primary phase by its first loop, thereby providing controller-level redundancy without a dedicated spare controller.
Regarding claim 5, as best understood, Barus does not disclose wherein the second loop comprises the image for operating the at least one phase.
However, ISL68137 teaches (see Fig. 1) wherein a loop comprises an image for operating a phase (each of the two regulation loops of Fig. 1 operates from per-output configuration data — output voltage set point, fault thresholds and phase assignment — that is held on-chip in the NVM block of Fig. 1 and loaded into that loop at power-up) (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “on-chip nonvolatile memory to store various configuration settings”; see p. 14 of ISL68137 “Output voltage set points and thresholds for each output can be configured”; and see p. 17 of ISL68137 “As many as eight configurations can be stored”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop comprises the image for operating the at least one phase, as taught by ISL68137, because holding in the second loop the image that Douglas copies from the first controller enables the second loop to regulate the at least one phase of the failed first controller from its own stored configuration, without waiting on an external management module at the time of the failure.
Regarding claim 10, Barus does not disclose wherein the second controller comprises a first loop and a second loop.
However, ISL68137 teaches (see Fig. 1) wherein the second controller (the ISL68137 digital dual output PWM controller) comprises a first loop (the Output 0 regulation loop of Fig. 1, comprising the VSEN0/RGND0 remote voltage sense inputs, VSA ADC, VDROOP, PID compensator and DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-0) and a second loop (the Output 1 regulation loop of Fig. 1, comprising the VSEN1/RGND1 remote voltage sense inputs, a second VSA ADC, VDROOP, PID compensator and a second DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-1), the two loops being arbitrated by the LOOP MANAGER of Fig. 1 (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “digital dual output, flexible multiphase (X+Y ≤ 7) PWM controller”; see p. 13 of ISL68137 “The ISL68137 supports up to two regulated outputs through seven configurable phases”; and see p. 17 of ISL68137 “the regulation loop is entirely digital”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas and Samii wherein the second controller comprises a first loop and a second loop, as taught by ISL68137, because it can permit a single controller to independently regulate two separate output rails, thereby providing a second, independently configurable regulation loop within the same controller and reducing the number of controllers required in the multiphase power subsystem of Barus.
Regarding claim 11, as best understood, Barus does not disclose wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop.
However, ISL68137 teaches (see Fig. 1 and Fig. 2) wherein the second controller (the ISL68137 digital dual output PWM controller) is configured to utilize a first loop (the Output 0 regulation loop of Fig. 1) to operate a primary phase (the phase driven by output PWM0 and sensed at CS0/CSRTN0, assigned to Output 0; Fig. 2 shows six such phases assigned to VOUT0) and a second loop (the Output 1 regulation loop of Fig. 1, which regulates VOUT1 and to which phases are separately assigned; Fig. 2 shows the phase driven by output PWM6 assigned to VOUT1) (see p. 6, Fig. 2 of ISL68137; see p. 13 of ISL68137 “Either output is capable of controlling up to seven phases in any arbitrary mix”; and see p. 13 of ISL68137 “For Output 0, phases would be assigned starting from Phase 0”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas and Samii wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop, as taught by ISL68137, because it can permit the phase already assigned to the second controller to remain regulated by the first loop while leaving the second loop separately configurable, thereby providing an independent regulation path within the second controller without adding a further controller to the power subsystem of Barus.
Barus does not disclose wherein the second loop serves as a backup to the first controller.
However, Samii teaches (see Fig. 3) a control entity that serves as a backup to the first controller (second controller 14, which operates in a hot standby status mode and is reconfigured to primary status upon a failure of the first controller 12) (see [0030] of Samii “the second controller 14 will be reconfigured as the primary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop serves as a backup to the first controller, as taught by Samii, because the second loop is an independent regulation path that is not committed to the primary phase, and assigning to it the hot standby backup role of Samii permits the second controller to assume the at least one phase of the failed first controller without interrupting regulation of the primary phase by its first loop, thereby providing controller-level redundancy without a dedicated spare controller.
Regarding claim 12, as best understood, Barus does not disclose wherein the second loop comprises the image for operating the at least one phase.
However, ISL68137 teaches (see Fig. 1) wherein a loop comprises an image for operating a phase (each of the two regulation loops of Fig. 1 operates from per-output configuration data — output voltage set point, fault thresholds and phase assignment — that is held on-chip in the NVM block of Fig. 1 and loaded into that loop at power-up) (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “on-chip nonvolatile memory to store various configuration settings”; see p. 14 of ISL68137 “Output voltage set points and thresholds for each output can be configured”; and see p. 17 of ISL68137 “As many as eight configurations can be stored”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control switch of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop comprises the image for operating the at least one phase, as taught by ISL68137, because holding in the second loop the image that Douglas copies from the first controller enables the second loop to regulate the at least one phase of the failed first controller from its own stored configuration, without waiting on an external management module at the time of the failure.
Regarding claim 17, Barus does not disclose wherein the second controller comprises a first loop and a second loop.
However, ISL68137 teaches (see Fig. 1) wherein the second controller (the ISL68137 digital dual output PWM controller) comprises a first loop (the Output 0 regulation loop of Fig. 1, comprising the VSEN0/RGND0 remote voltage sense inputs, VSA ADC, VDROOP, PID compensator and DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-0) and a second loop (the Output 1 regulation loop of Fig. 1, comprising the VSEN1/RGND1 remote voltage sense inputs, a second VSA ADC, VDROOP, PID compensator and a second DIGITAL DUAL EDGE MODULATOR, with phase current feedback ISUM-1), the two loops being arbitrated by the LOOP MANAGER of Fig. 1 (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “digital dual output, flexible multiphase (X+Y ≤ 7) PWM controller”; see p. 13 of ISL68137 “The ISL68137 supports up to two regulated outputs through seven configurable phases”; and see p. 17 of ISL68137 “the regulation loop is entirely digital”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas and Samii wherein the second controller comprises a first loop and a second loop, as taught by ISL68137, because it can permit a single controller to independently regulate two separate output rails, thereby providing a second, independently configurable regulation loop within the same controller and reducing the number of controllers required in the multiphase power subsystem of Barus.
Regarding claim 18, as best understood, Barus does not disclose wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop.
However, ISL68137 teaches (see Fig. 1 and Fig. 2) wherein the second controller (the ISL68137 digital dual output PWM controller) is configured to utilize a first loop (the Output 0 regulation loop of Fig. 1) to operate a primary phase (the phase driven by output PWM0 and sensed at CS0/CSRTN0, assigned to Output 0; Fig. 2 shows six such phases assigned to VOUT0) and a second loop (the Output 1 regulation loop of Fig. 1, which regulates VOUT1 and to which phases are separately assigned; Fig. 2 shows the phase driven by output PWM6 assigned to VOUT1) (see p. 6, Fig. 2 of ISL68137; see p. 13 of ISL68137 “Either output is capable of controlling up to seven phases in any arbitrary mix”; and see p. 13 of ISL68137 “For Output 0, phases would be assigned starting from Phase 0”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas and Samii wherein the second controller is configured to utilize a first loop to operate a primary phase and a second loop, as taught by ISL68137, because it can permit the phase already assigned to the second controller to remain regulated by the first loop while leaving the second loop separately configurable, thereby providing an independent regulation path within the second controller without adding a further controller to the power subsystem of Barus.
Barus does not disclose wherein the second loop serves as a backup to the first controller.
However, Samii teaches (see Fig. 3) a control entity that serves as a backup to the first controller (second controller 14, which operates in a hot standby status mode and is reconfigured to primary status upon a failure of the first controller 12) (see [0030] of Samii “the second controller 14 will be reconfigured as the primary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop serves as a backup to the first controller, as taught by Samii, because the second loop is an independent regulation path that is not committed to the primary phase, and assigning to it the hot standby backup role of Samii permits the second controller to assume the at least one phase of the failed first controller without interrupting regulation of the primary phase by its first loop, thereby providing controller-level redundancy without a dedicated spare controller.
Regarding claim 19, as best understood, Barus does not disclose wherein the second loop comprises the image for operating the at least one phase.
However, ISL68137 teaches (see Fig. 1) wherein a loop comprises an image for operating a phase (each of the two regulation loops of Fig. 1 operates from per-output configuration data — output voltage set point, fault thresholds and phase assignment — that is held on-chip in the NVM block of Fig. 1 and loaded into that loop at power-up) (see p. 5, Fig. 1 of ISL68137; see p. 1 of ISL68137 “on-chip nonvolatile memory to store various configuration settings”; see p. 14 of ISL68137 “Output voltage set points and thresholds for each output can be configured”; and see p. 17 of ISL68137 “As many as eight configurations can be stored”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the second loop comprises the image for operating the at least one phase, as taught by ISL68137, because holding in the second loop the image that Douglas copies from the first controller enables the second loop to regulate the at least one phase of the failed first controller from its own stored configuration, without waiting on an external management module at the time of the failure.
Regarding claim 20, as best understood, Barus does not disclose wherein the first controller comprises an original image for operating the at least one phase; and the second controller comprises the image as a copy of the original image of the first controller.
However, Douglas teaches (see Fig. 2, Fig. 3, and Fig. 4) wherein the first controller (primary controller 104) comprises an original image for operating the at least one phase (see [0017] of Douglas “a firmware image written by a management module to a first memory device of the primary controller”); and the second controller (secondary controller 106) comprises the image as a copy of the original image of the first controller (see [0017] of Douglas “to write a copy of the firmware image to a second memory device of the secondary controller”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Barus as modified in view of Douglas, Samii, and ISL68137 wherein the first controller comprises an original image for operating the at least one phase and the second controller comprises the image as a copy of the original image of the first controller, as taught by Douglas, because Barus already requires the surviving phase controller to operate the failed controller’s phase from the same control values (see [0022] of Barus “The remaining N+1 phase controllers receive the same PVID values”), and Douglas provides the mechanism by which the controller to be duplicated holds an original image and the redundant peer holds a copy of that original image, so that applying that arrangement in Barus predictably yields a second controller that operates the at least one phase in the same manner as the failed first controller.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 11,133,745 B2 discloses automatic power-on-reset detection and recovery of a multi-phase digital buck controller having a plurality of controllers communicating over an onboard bus.
US 2016/0165463 A1 discloses stand-by controller assisted failover in which a standby controller takes over for an active controller upon a detected failure.
US 10,734,914 B2 discloses a fault-tolerant controller for a modular multi-level converter in which a controller detects a fault in an adjacent power module and initiates reconfiguration.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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