Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sakariya et al. (US App. 20140168037 hereinafter referred to as “Saka”).
In regard to claim 1, Saka teaches an array substrate (See at least Abstract and Fig. 1, Abstract), comprising: a driver circuit comprising at least two output pins (see Fig. 1, microcontroller IC 110); and a device unit connected to an output pin of the driver circuit, wherein any one of a plurality of device units comprises a functional element or a plurality of electrically connected functional elements, and different device units of the plurality of device units are connected to different output pins of a same driver circuit, or to output pins of different driver circuits (see Fig. 1, and Para. 32 different pins of 110 connected to different RGB LEDs); wherein a first driver circuit in a first area has a first position relationship with a device unit to which the first driver circuit is connected, and a second driver circuit in a second area has a second position relationship with a device unit to which the second driver circuit is connected, the first area being adjacent to the second area, the first position relationship being different from the second position relationship (see Fig. 1, different microcontroller ICs 110 at different locations while also adjacent in the matrix 100).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya et al. (US App. 20140168037 hereinafter referred to as “Saka”)
Regarding claim 2, Saka teaches all the limitations of claim 1. Saka further teaches wherein the driver circuit further comprises: a ground pin configured to load a ground voltage to the driver circuit (see Fig. 1, pin to Vss bus); a chip power supply pin configured to load a chip power supply voltage to the driver circuit for driving the operation of the driver circuit (see Fig. 1, pin to Vdd bus). That Saka embodiment is not relied upon to teach an address pin configured to receive an address signal; a relay pin; wherein the driving data comprises address information and driving information; a logic control circuit; and a data pin configured to receive driving data.
However, other embodiments of Saka teach an address pin configured to receive an address signal (see Figs. 1 and 9, address information); a relay pin (see Para. 63); wherein the driving data comprises address information and driving information (see Para. 55, address information in data); a logic control circuit (see Para. 8 and 50, synchronization logic); and a data pin configured to receive driving data (see Fig. 1 data).
It would have been obvious to a person of ordinary skill in the art to modify the microcontroller of Saka to include the logic of Saka such that multiple LEDs can be controlled with one microcontroller (See Para. 7.) Examiner also notes Saka discloses the base product/process of microcontrollers while Saka teaches the known technique of various signals for pins on the microcontroller so as to yield predictable results of varying control in the microcontroller and its I/O in the display device of Saka.
Allowable Subject Matter
Claims 3-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Zhang et al. (US App. 20210343213) and Park et al. (US App. 20220172672) discloses the concept of LEDs at the corner pins; Zhao et al. (US App. 20240038946) discloses the concept of two pin rows with one of 5 pins; and Wei et al. (US App. 20210366391) has target address matching.
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/MATTHEW YEUNG/ Primary Examiner, Art Unit 2625