DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
EXAMINER'S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
The application has been amended as follows:
Claims 2-3 are cancelled [See Remarks: pg. 6, 1st – 3rd para.; “Accordingly, Claims 2 and 3 are hereby canceled without prejudice or disclaimer.”].
Response to Arguments
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
Regarding the rejection of claim 1, the Applicant argues [Remarks: pg. 7, 1st – 2nd para.], that “The Examiner admits that the cited disclosure of Takei does not teach "the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value" as recited in Claim 3, and relies upon the disclosure of Nagase to cure the admitted deficiencies of Takei. However, Nagase does not disclose, teach, or suggest "the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value to be written to the all pixels in the preset period that is followed by the write period, the response period, and the light emission period" as presently recited in Claim 1.
Thus, Applicant respectfully submits that the asserted combination of Takei and Nagase does not disclose or teach each and every recited element of Claim 1 as currently amended. Accordingly, Applicant respectfully submits that independent Claim 1 is patentably distinguished from the cited prior art and is currently in condition for allowance. Therefore, Applicant respectfully requests withdrawal of the present rejection of independent Claim 1.”
The Office respectfully disagrees.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Refer to figure 8 of Takei, which explicitly shows a reset period [corresponding to claimed preset period], a write period, a response period, and a light-source on period [corresponding to claimed light emission period]. The response period utilized to allow for time for all pixels to achieve the correct alignment state corresponding to the applied voltage [see para. 85].
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches amended independent claim 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 & 4-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takei (US 20030098836), in view of Nagase (US 20040189586).
As to claim 1, Takei discloses a display device (field sequential type liquid crystal display apparatus) [abstract & figs. 1-3 & 6] comprising:
a display panel (liquid crystal display device 10) [figs. 1-3 & 6 & para. 47-48] having a display area in which a plurality of pixels (plurality of pixels laid out in matrix form) [figs. 1-3 & 6 & para. 47] are arrayed in a first direction and a second direction orthogonal to the first direction;
a light source (illumination device 40 comprising light sources 42r, 42g and 42b) [figs. 1 & 6 & para. 47] configured to output light to the display panel; and
a signal processing circuit (control section 77) [fig. 6 & para. 76] configured to control the display panel and the light source (illumination device 40 controlled by illumination control section 76 controlled by control section 77) [para. 76], wherein
the signal processing circuit sets a preset gradation value (reset voltage) [figs. 7-8 & para. 77-79, 83-85, & 58-59] written to all pixels in the display area based on a frame image of one frame (field) [figs. 7-8 & para. 77-79 & 83-85] to be displayed in the display area,
the display panel has:
a preset period (reset period) [figs. 7-8 & para. 77-79 & 83-85] for writing the preset gradation value to all pixels in the display area;
a write period (write period) [figs. 7-8 & para. 77-79 & 83-85] for writing a gradation value for each pixel of the frame image in one frame period for displaying the frame image after the preset period; and
a light emission period (emission period where light sources are activated in sequence) [figs. 7-8 & para. 77-79 & 83-85] for lighting up the light source when a predetermined response period has elapsed after the gradation value for each pixel of the frame image is written (after passage of a time after writing) [figs. 7-8 & para. 78 & 84-85], and
the signal processing circuit sets a value of the gradation values (reset voltage utilize data voltage v1 corresponding to one of nine gradations) [fig. 7-8 & para. 68, 77-79, 83-85, & 58-59] for the respective pixels of the frame image as the preset gradation value to be written to the all pixels in the preset period (reset period) [figs. 7-8 & para. 77-79, 83-85, & 58-59] that is followed by the write period (write period) [figs. 7-8 & para. 77-79, 83-85, & 58-59], the response period (response period) [figs. 7-8 & para. 77-79, 83-85, & 58-59], and the light emission period (light-source on period) [figs. 7-8 & para. 77-79, 83-85, & 58-59].
Takei does not explicitly teach the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
As to claim 4, Takei as modified by Nagase teaches the display device according to claim 1, wherein the signal processing circuit sets the preset gradation value to a minimum gradation value of the display panel when the gradation values of all pixels of the frame image are the minimum gradation value (Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 5, Takei as modified by Nagase teaches the display device according to claim 1, wherein the signal processing circuit sets the preset gradation value to a maximum gradation value of the display panel when the gradation values of all pixels of the frame image are the maximum gradation value (Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 6, Takei as modified by Nagase teaches the display device according to claim 1, wherein one frame period for displaying the frame image includes a plurality of sub-field periods for displaying different colors (r field, g field, & b field) [Takei: figs. 7-8 & para. 77-79 & 83-85].
As to claim 7, Takei as modified by Nagase teaches the display device according to claim 6, wherein the sub-field periods include:
a first sub-field period for displaying a first color (red) [Takei: figs. 7-8 & para. 77-79, 47, & 83-85];
a second sub-field period for displaying a second color (green) [Takei: figs. 7-8 & para. 77-79, 47, & 83-85]; and
a third sub-field period for displaying a third color (blue) [Takei: figs. 7-8 & para. 77-79, 47, & 83-85].
As to claim 8, Takei as modified by Nagase teaches the display device according to claim 7, wherein the light source comprises:
a first light emitter configured to emit light of the first color (light source 42r) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85];
a second light emitter configured to emit light of the second color (light source 42g) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85]; and
a third light emitter configured to emit light of the third color (light source 42b) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 9, Takei as modified by Nagase teaches the display device according to claim 8, wherein the display panel has the light emission period for lighting up the first light emitter when the predetermined response period has elapsed after the gradation value of the first color for each pixel of the frame image is written in the first sub-field period (r field) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 10, Takei as modified by Nagase teaches the display device according to claim 9, wherein the signal processing circuit sets the average value of the gradation values for the respective pixels of the first color of the frame image as the preset gradation value in the first sub-field period (r field) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 11, Takei as modified by Nagase teaches the display device according to claim 9, wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a minimum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the minimum gradation value (r field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 12, Takei as modified by Nagase teaches the display device according to claim 9, wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a maximum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the maximum gradation value r field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 13, Takei as modified by Nagase teaches the display device according to any one of claim 10, wherein the display panel has a preset period for writing the preset gradation value in the first sub-field period to all pixels in the display area before a write period for writing the gradation value of the first color for each pixel of the frame image in the first sub-field period (reset period for r field) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 14, Takei as modified by Nagase teaches the display device according to claim 8, wherein the display panel has the light emission period for lighting up the second light emitter when the predetermined response period has elapsed after the gradation value of the second color for each pixel of the frame image is written in the second sub-field period (g field) [figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 15, Takei as modified by Nagase teaches the display device according to claim 14, wherein the signal processing circuit sets the average value of the gradation values for the respective pixels of the second color of the frame image as the preset gradation value in the second sub-field period g field) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 16, Takei as modified by Nagase teaches the display device according to claim 14, wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a minimum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the minimum gradation value (g field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 17, Takei as modified by Nagase teaches the display device according to claim 14, wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a maximum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the maximum gradation value (g field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
As to claim 18, Takei as modified by Nagase teaches the display device according to any one of claim 15, wherein the display panel has a preset period for writing the preset gradation value to all pixels in the display area before a write period for writing the gradation value of the second color for each pixel of the frame image in the second sub-field period (reset period for g field) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 19, Takei as modified by Nagase teaches the display device according to claim 8, wherein the display panel has the light emission period for lighting up the third light emitter when the predetermined response period has elapsed after the gradation value of the third color for each pixel of the frame image is written in the third sub-field period (b field) [Takei: figs. 1-8 & para. 77-79, 47, & 83-85].
As to claim 20, Takei as modified by Nagase teaches the display device according to claim 19, wherein the signal processing circuit sets the average value of the gradation values for the respective pixels of the third color of the frame image as the preset gradation value in the third sub-field period (b field) [Takei: figs. 7-8 & para. 77-79 & 83-85 & Nagase: para. 105-106].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
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/DAVID TUNG/Primary Examiner, Art Unit 2622
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