DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species I [figures 1-2 & 6-9d, corresponding to claims 1-20] in the reply filed on 2/19/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/6/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-9, 14, & 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takei (US 20030098836).
As to claim 1, Takei discloses a display device (field sequential type liquid crystal display apparatus) [abstract & figs. 1-3 & 6] comprising:
a display panel (liquid crystal display device 10) [figs. 1-3 & 6 & para. 47-48] having a display area in which a plurality of pixels (plurality of pixels laid out in matrix form) [figs. 1-3 & 6 & para. 47] are arrayed in a first direction and a second direction orthogonal to the first direction;
a light source (illumination device 40 comprising light sources 42r, 42g and 42b) [figs. 1 & 6 & para. 47] configured to output light to the display panel; and
a signal processing circuit (control section 77) [fig. 6 & para. 76] configured to control the display panel and the light source (illumination device 40 controlled by illumination control section 76 controlled by control section 77) [para. 76], wherein
the signal processing circuit sets a preset gradation value (reset voltage) [fig. 7 & para. 77-79, 83, & 58-59] written to all pixels in the display area based on a frame image of one frame (field) [fig. 7 & para. 77-79 & 83] to be displayed in the display area, and
the display panel has a preset period (reset period) [fig. 7 & para. 77-79 & 83] for writing the preset gradation value to all pixels in the display area before a write period (write period) [fig. 7 & para. 77-79 & 83] for writing a gradation value for each pixel of the frame image in one frame period for displaying the frame image.
As to claim 2, Takei discloses the display device according to claim 1, wherein the display panel has a light emission period (emission period where light sources are activated in sequence) [fig. 7 & para. 77-79 & 83] for lighting up the light source when a predetermined response period has elapsed after the gradation value for each pixel of the frame image is written (after passage of a time after writing) [fig. 7 & para. 78].
As to claim 6, Takei discloses the display device according to claim 1, wherein one frame period for displaying the frame image includes a plurality of sub-field periods for displaying different colors (r field, g field, & b field) [fig. 7 & para. 77-79 & 83].
As to claim 7, Takei discloses the display device according to claim 6, wherein the sub-field periods include:
a first sub-field period for displaying a first color (red) [fig. 7 & para. 77-79, 47, & 83];
a second sub-field period for displaying a second color (green) [fig. 7 & para. 77-79, 47, & 83]; and
a third sub-field period for displaying a third color (blue) [fig. 7 & para. 77-79, 47, & 83].
As to claim 8, Takei discloses the display device according to claim 7, wherein the light source comprises:
a first light emitter configured to emit light of the first color (light source 42r) [figs. 1-7 & para. 77-79, 47, & 83];
a second light emitter configured to emit light of the second color (light source 42g) [figs. 1-7 & para. 77-79, 47, & 83]; and
a third light emitter configured to emit light of the third color (light source 42b) [figs. 1-7 & para. 77-79, 47, & 83].
As to claim 9, Takei discloses the display device according to claim 8, wherein the display panel has a light emission period for lighting up the first light emitter when a predetermined response period has elapsed after the gradation value of the first color for each pixel of the frame image is written in the first sub-field period (r field) [figs. 1-7 & para. 77-79, 47, & 83].
As to claim 14, Takei discloses the display device according to claim 8, wherein the display panel has a light emission period for lighting up the second light emitter when a predetermined response period has elapsed after the gradation value of the second color for each pixel of the frame image is written in the second sub-field period (g field) [figs. 1-7 & para. 77-79, 47, & 83].
As to claim 19, Takei discloses the display device according to claim 8, wherein the display panel has a light emission period for lighting up the third light emitter when a predetermined response period has elapsed after the gradation value of the third color for each pixel of the frame image is written in the third sub-field period (b field) [figs. 1-7 & para. 77-79, 47, & 83].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-5, 10-13, 15-18, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takei, in view of Nagase (US 20040189586).
As to claim 3, Takei teaches the display device according to claim 1 (See above).
Takei does not explicitly teach wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
As to claim 4, Takei teaches the display device according to claim 1 (See above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value to a minimum gradation value of the display panel when the gradation values of all pixels of the frame image are the minimum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value to a minimum gradation value of the display panel when the gradation values of all pixels of the frame image are the minimum gradation value (Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 5, Takei teaches the display device according to claim 1 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value to a maximum gradation value of the display panel when the gradation values of all pixels of the frame image are the maximum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value to a maximum gradation value of the display panel when the gradation values of all pixels of the frame image are the maximum gradation value (Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 10, Takei teaches the display device according to claim 9 (See above).
Takei does not explicitly teach wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the first color of the frame image as the preset gradation value in the first sub-field period.
Takei does not explicitly teach wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the first color of the frame image as the preset gradation value in the first sub-field period.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the first color of the frame image as the preset gradation value in the first sub-field period (r field) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 11, Takei teaches the display device according to claim 9 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a minimum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the minimum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a minimum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the minimum gradation value (r field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 12, Takei teaches the display device according to claim 9 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a maximum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the maximum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value in the first sub-field period to a maximum gradation value of the display panel when the gradation values of the first color of all pixels of the frame image are the maximum gradation value (r field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 13, Takei as modified by Nagase teaches the display device according to any one of claim 10, wherein the display panel has a preset period for writing the preset gradation value in the first sub-field period to all pixels in the display area before a write period for writing the gradation value of the first color for each pixel of the frame image in the first sub-field period (reset period for r field) [Takei: figs. 1-7 & para. 77-79, 47, & 83].
As to claim 15, Takei teaches the display device according to claim 14 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the second color of the frame image as the preset gradation value in the second sub-field period.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the second color of the frame image as the preset gradation value in the second sub-field period (g field) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 16, Takei teaches the display device according to claim 14 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a minimum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the minimum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a minimum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the minimum gradation value (g field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all white screen [lowest gradation value 0], the averaged value for the preset gradation value corresponding to the of an all white screen would be the minimum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 17, Takei teaches the display device according to claim 14 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a maximum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the maximum gradation value.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets the preset gradation value in the second sub-field period to a maximum gradation value of the display panel when the gradation values of the second color of all pixels of the frame image are the maximum gradation value (g field, Takei teaches a normally white display, thus, when displaying an image of one gradation such as an all black screen [highest gradation value 255], the averaged value for the preset gradation value corresponding to the of an all black screen would be the maximum gradation value) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
As to claim 18, Takei as modified by Nagase teaches the display device according to any one of claim 15, wherein the display panel has a preset period for writing the preset gradation value to all pixels in the display area before a write period for writing the gradation value of the second color for each pixel of the frame image in the second sub-field period (reset period for g field) [Takei: figs. 1-7 & para. 77-79, 47, & 83].
As to claim 20, Takei teaches the display device according to claim 19 (see above).
Takei does not explicitly teach wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the third color of the frame image as the preset gradation value in the third sub-field period.
Nagase teaches the concept of a display device [abstract & figs. 15-16 & para. 101-108], wherein a signal processing circuit (arithmetic unit) [figs. 15-16 & para. 101-108] sets an average value of gradation values [para. 105-106] for respective pixels of a frame image as a preset gradation value (pre-writing data voltage) [para. 105-106].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the signal processing circuit of the display device of Takei, such that the signal processing circuit sets an average value of the gradation values for the respective pixels of the frame image as the preset gradation value, as taught by Nagase, to improve writing efficiency and reduce cost, as taught by Nagase [para. 107].
Thus, Takei as modified by Nagase teaches wherein the signal processing circuit sets an average value of the gradation values for the respective pixels of the third color of the frame image as the preset gradation value in the third sub-field period (b field) [Takei: fig. 7 & para. 77-79 & 83 & Nagase: para. 105-106].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyatake et al. (US 20140062984).
Park (US 20050253796).
Aoki et al. (US 20180240424).
Waterman (US 20020075221).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571)-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID TUNG/Primary Examiner, Art Unit 2622
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