Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20210125678 A1) in view of Mohan (US 4597805 A), in further view of Lee et al. (US 20030021154 A1).
Regarding claim 1: Cho discloses an electronic fuse cell array structure (10, FIG. 1) comprising: an eFuse cell array (60, FIG. 1A) in which unit cells (e.g., unit cells 100a and 100b, FIG. 1C and 4) of different types are alternately disposed (par. 82 and 157), wherein a first type unit cell and a second type unit cell are connected to each other via a common node (bit line BL acts as common node, e.g., between unit cells 110 and 110b of FIG. 4; also node N3 of FIG. 2 matching claimed invention), and a guard ring (150, FIG. 2).
Cho does not disclose a guard ring disposed to surround the first type unit cell and the second type unit cell.
Mohan does disclose a memory device with a guard ring (FIG. 1) for reducing pattern sensitivity, comprising: a guard ring disposed to surround the first type unit cell and the second type unit cell (guard ring 20 surrounding entire cell array 10, FIG 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Cho with the guard ring configuration of Mohan to allow the guard ring to be fitted to surround the two unit cells as in the claimed invention to make insolate and ensure a more efficient operation.
Cho and Mohan do not disclose a common node discharge circuit connected to the common node and configured to discharge a voltage charged to the common node in response to control signals according to an operation mode of the memory device.
Lee does disclose a discharge circuit and method for erase discharge of memory device (FIG. 1) comprising: a common node discharge circuit (latch circuit 130, FIG. 1) connected to the common node (VIRPWR on all bit lines, par. 71, FIG. 1) and configured to discharge a voltage charged to the common node (discharge bitlines, par. 70) in response to control signals (e.g., PCTLN and VBLe, par. 67-70) according to an operation mode (e.g., programming/setup, par. 67-70) of the memory device.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho and Mohan with the discharge circuit of Lee to allow the system to help discharge excess voltage applied to the unit cells to help prevent blown fuses.
Regarding claim 3: Cho discloses an electronic fuse cell array structure (10, FIG. 1), wherein the guard ring is a highly doped p-type doped region (P-type guard ring 150, par. 93, FIG. 2).
Regarding claim 4: Cho discloses an electronic fuse cell array structure (10, FIG. 1), further comprising: a first PMOS transistor (PMOS transistor 210, FIG. 2 and 4) disposed outside the unit cells (FIG. 2 and 4) and configured to supply a program current (programming current, FIG. 4) to the first type unit cell and the second type unit cell (e.g., 110 and 110b of FIG. 4) via the common node (common node of bitline BL of FIG. 4 or N3 of Fig 2, connected to PMOS transistor 210), wherein the first PMOS transistor comprises a gate terminal connected to a line configured to receive a fuse blowing-bar (BLOWB) signal obtained by inverting a fuse blowing signal (gate of PMOS transistor 210 configured to receive a program signal, par. 98, FIG. 4), a source terminal connected to a power supply voltage (source of PMOS transistor 210 connected to program voltage VDD, par. 98), and a drain terminal connected to the common node (drain of PMOS transistor 210 coupled to node N3, par. 98, FIG. 2).
Regarding claim 5: Cho discloses an electronic fuse cell array structure (10, FIG. 1), further comprising: a first NMOS transistor (NMOS transistor 140, FIG. 2 and 4) disposed outside the unit cells (FIG. 2 and 4) and configured to operatively connect the first type unit cell and the second type unit cell (e.g., 110 and 110b of FIG. 4) to a ground via the common node (common node of bitline BL of FIG. 4 or N3 of Fig 2, source of transistor 140 configured to be coupled to reference voltage VSS or ground, par. 99, FIG. 2 and 4), wherein the first NMOS transistor comprises a gate terminal (gate of NMOS transistor 140, FIG. 2 and 4) connected to a line configured to receive a read mode (RD) signal (read enable signal, par. 99) indicating whether a read mode is present, a drain terminal connected to the common node (drain of NMOS transistor 140 connected to common node N3, par. 99, FIG. 2), and a source terminal connected to the ground (par. 99, FIG. 2 and 4).
Regarding claim 6: Cho discloses an electronic fuse cell array structure (10, FIG. 1), further comprising: a program driver (programming driver 50, FIG. 1A) configured to supply a program current to the common node of a selected column among columns of the eFuse cell array (PD driver 50 configured to supply programming current to bitlines of eFuse cell array 60, par. 66); and a sense amplifier (70, FIG. 1) configured to read data of any one unit cell among unit cells of the selected column based on a voltage (sense amplifier configured to detect whether an eFuse is blown, checking a change in voltage, par. 66 and 134) of a bit line of the selected column.
Regarding claim 11: Cho and Mohan do not disclose a memory device, wherein the common node discharge circuit is disposed outside the unit cells.
Lee does disclose a discharge circuit and method for erase discharge of memory device (FIG. 1) comprising: wherein the common node discharge circuit is disposed outside the unit cells (latch circuits for discharging are located outside the array 110, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Cho and Mohan with the configuration of Lee to allow the discharge circuit to be outside the unit cell array as the claimed invention.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20210125678 A1) in view of Mohan (US 4597805 A), in further view of Lee et al. (US 20030021154 A1), in further view of Liao et al. (US 20130100756 A1).
Regarding claim 2: Cho, Mohan, and Lee do not disclose a memory device, wherein the first type unit cell and the second type unit cell, which are disposed side by side in a horizontal direction with respect to the common node to form a bilaterally symmetrical structure, are connected to a same bit line.
Liao does disclose a mechanism of reconfiguring an eFuse memory array (FIG. 2A), wherein the first type unit cell (eFuse memory cell MC[0,0]’, FIG. 2A) and the second type unit cell (eFuse memory cell MC[0,1]’, FIG. 2A), which are disposed side by side in a horizontal direction (side by side horizontally, par. 36, FIG. 2A) with respect to the common node to form a bilaterally symmetrical structure, are connected to a same bit line (eFuse cells symmetrical with a connecting bit line BLP[0]′, par. 36, FIG. 2A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho, Mohan, and Lee with the configuration of Liao to allow the cell array to be a more uniform and symmetrical structure, allowing program bit lines to be shortened by about half for more efficient area.
Claim(s) 12, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20210125678 A1) in view of Lee et al. (US 20030021154 A1).
Regarding claim 12: Cho discloses an electronic fuse cell array structure (10, FIG. 1), comprising: an eFuse cell array (60, FIG. 1A) in which unit cells of different types cells (e.g., unit cells 100a and 100b, FIG. 1C and 4) are alternately disposed (par. 82 and 157), wherein a first type unit cell and a second type unit cell are connected to each other via a common node (bit line BL acts as common node, e.g., between unit cells 110 and 110b of FIG. 4; also node N3 of FIG. 2 matching claimed invention).
Cho does not disclose a common node discharge circuit connected to the common node and comprising a first NMOS transistor connected between the common node and a ground, wherein the common node discharge circuit is configured to discharge a voltage charged to the common node in response to control signals according to an operation mode of the memory device.
Lee does disclose a discharge circuit and method for erase discharge of memory device (FIG. 1) comprising: a common node discharge circuit (latch circuit 130, FIG. 1) connected to the common node (VIRPWR on all bit lines, par. 71, FIG. 1) and comprising a first NMOS transistor (NMOS transistor 304, FIG. 5) connected between the common node (VIRPWRP, FIG. 5) and a ground (GND, FIG. 5), wherein the common node discharge circuit is configured to discharge a voltage charged to the common node (discharge bitlines, par. 70) in response to control signals (e.g., PCTLN and VBLe, par. 67-70) according to an operation mode (e.g., programming/setup, par. 67-70) of the memory device.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho with the discharge circuit of Lee to allow the system to help discharge excess voltage applied to the unit cells to help prevent blown fuses like the claimed invention.
Regarding claim 15: Cho discloses an electronic fuse cell array structure (10, FIG. 1), further comprising: a program driver (programming driver 50, FIG. 1A) configured to supply a program current to the common node of a selected column among columns of the eFuse cell array (PD driver 50 configured to supply programming current to bitlines of eFuse cell array 60, par. 66); and a sense amplifier (70, FIG. 1) configured to read data of any one unit cell among unit cells of the selected column based on a voltage (sense amplifier configured to detect whether an eFuse is blown, checking a change in voltage, par. 66 and 134) of a bit line of the selected column.
Regarding claim 18: Cho does not disclose a memory device, wherein, when the operation mode of the memory device is standby mode or '0' program mode, the common node discharge circuit is configured to discharge the voltage charged to the common node by turning on the first NMOS transistor.
Lee does disclose a discharge circuit and method for erase discharge of memory device (FIG. 1), wherein, when the operation mode of the memory device is standby mode or ‘0’ program mode (via state machine that controls control signals, par. 55), the common node discharge circuit is configured to discharge the voltage charged to the common node (discharge VIRPWRP to 0V, par. 58) by turning on the first NMOS transistor (turn on NMOS 304, par. 58).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Cho with the configuration of Lee to allow the system to operate the circuit discharge similar to the claimed invention.
Regarding claim 20: Cho does not disclose a memory device, wherein the common node discharge circuit is disposed outside the unit cells wherein the common node discharge circuit is disposed outside the unit cells.
Lee does disclose a discharge circuit and method for erase discharge of memory device (FIG. 1), wherein the common node discharge circuit is disposed outside the unit cells wherein the common node discharge circuit is disposed outside the unit cells (latch circuits for discharging are located outside the array 110, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Cho with the configuration of Lee to allow the discharge circuit to be outside the unit cell array as the claimed invention.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20210125678 A1) in view of Lee et al. (US 20030021154 A1), in further view of Liao et al. (US 20130100756 A1).
Regarding claim 13: Cho and Lee do not disclose a memory device, wherein the first type unit cell and the second type unit cell, which are disposed side by side in a horizontal direction with respect to the common node to form a bilaterally symmetrical structure, are connected to a same bit line.
Liao does disclose a mechanism of reconfiguring an eFuse memory array (FIG. 2A), wherein the first type unit cell (eFuse memory cell MC[0,0]’, FIG. 2A) and the second type unit cell (eFuse memory cell MC[0,1]’, FIG. 2A), which are disposed side by side in a horizontal direction (side by side horizontally, par. 36, FIG. 2A) with respect to the common node to form a bilaterally symmetrical structure, are connected to a same bit line (eFuse cells symmetrical with a connecting bit line BLP[0]′, par. 36, FIG. 2A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Cho, Mohan, and Lee with the configuration of Liao to allow the cell array to be a more uniform and symmetrical structure, allowing program bit lines to be shortened by about half for more efficient area.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20210125678 A1) in view of Lee et al. (US 20030021154 A1), in further view of Mohan (US 4597805 A).
Regarding claim 14: Cho discloses an electronic fuse cell array structure (10, FIG. 1), further comprising: a p-type guard ring (P-type guard ring 150, par. 93, FIG. 2); a first PMOS transistor (PMOS transistor 210, FIG. 2 and 4) disposed outside the unit cells (FIG. 2 and 4) and configured to supply a program current (programming current, FIG. 4) to the first type unit cell and the second type unit cell (e.g., 110 and 110b of FIG. 4) via the common node (common node of bitline BL of FIG. 4 or N3 of Fig 2, connected to PMOS transistor 210); and a second NMOS transistor (NMOS transistor 140, FIG. 2 and 4) disposed outside the unit cells and configured to operatively connect the first type unit cell and the second type unit cell (e.g., unit cells 100a and 100b, FIG. 1C and 4) to the ground via the common node (common node of bitline BL of FIG. 4 or N3 of Fig 2, source of transistor 140 configured to be coupled to reference voltage VSS or ground, par. 99, FIG. 2 and 4).
Cho does not disclose a guard ring disposed to surround the first type unit cell and the second type unit cell.
Mohan does disclose a memory device with a guard ring (FIG. 1) for reducing pattern sensitivity, comprising: a guard ring disposed to surround the first type unit cell and the second type unit cell (guard ring 20 surrounding entire cell array 10, FIG 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Cho and Lee with the guard ring configuration of Mohan to allow the guard ring to be fitted to surround the two unit cells as in the claimed invention to make insolate and ensure a more efficient operation.
Allowable Subject Matter
Claims 7-10, 16-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: the configuration of a discharge circuit wherein a second NMOS transistor comprising a gate terminal connected to a sense amplifier, a drain terminal connected to the common node, and a source terminal connected to a ground, and configured to turn on or off in response to the control signals as in claim 7; wherein the control signals comprise a read mode signal provided from the sense amplifier and indicating whether a read mode is present, and a fuse blowing-bar signal obtained by inverting a fuse blowing signal as in claims 9 and 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights