DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Danson et al. (US 2017/0264308).
Regarding claim 1, Danson discloses in figure 1 an ADC architecture that teaches:
a first analogue-to-digital converter (18, ADCa), arranged to sample an analogue input (IN) and produce a digital output (n) based on the sampled analogue Input; a second analogue-to-digital converter (18, ADCb), arranged to sample the analogue input (IN) and produce a digital output (n) based on the sampled analogue input; a signal interleaving portion (20), arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter to produce a digital output signal (Digital Out); the time-interleaved analogue-to-digital converter (10) configured for operation both in an operational mode ("Naturally, the control circuitry may be operable, when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried out by the core sub-ADC units of the set." (para. 0042), and in a compensation mode ("The control circuitry may be operable, when one of the core sub-ADC units of the set is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried out by the other core sub-ADC units of the set." (para. 0043), wherein the time-interleaved analogue-to-digital converter (10) is configured to operate in the compensation mode when the third analogue-to-digital converter is non-functional (NB without loss of generality it can be assumed that ADCc is the core sub-ADC unit that was determined to be defective, in the above-mapped example); wherein, in the operational mode, second analogue-to-digital converter (ADCA) is arranged to sample the analogue input (IN) at a first frequency ("... a rate at which they carry out the core conversion operations when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit.",(para 0043) and the second analogue-to-digital converter (ADCA) is arranged to sample the analogue input at a second frequency (NB it is implicit that all sub-ADCs in D1 operate at the same frequency in a given mode; in this case the first and second frequencies are identical); and wherein, in the calibration (or compensation) mode, the second analogue-to-digital converter (ADCA) is arranged to sample the analogue input at a third frequency ("... a faster rate than a rate at which they carry out the core conversion operations when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit", (para. 0043) and the second analogue-to- digital converter is arranged to sample the analogue input at a fourth frequency (NB it is implicit that all sub-ADCs in D1 operate at the same frequency in a given mode: in this case the third and fourth frequencies are identical), wherein the third frequency is higher than the first frequency ("a faster rate", (para. 0043), and wherein the fourth frequency is higher than the second frequency (NB since the first and second frequencies are identical and the third and fourth frequencies as well, consequently the fourth frequency is also higher than the second frequency, (para. 0043) (see figure 1 and its descriptions).
Regarding claim 2, Danson also teaches wherein in the calibration mode the second analogue-to-digital converter (ADC2)is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter sampling the analogue input.
Regarding claim 3, Danson also teaches wherein the time-interleaved analogue-to-digital converter (10) is configured for operation in the calibration mode during a period of time in which an expected value of the analogue input is known.
Regarding claim 4, Danson also teaches wherein the time-interleaved analogue-to-digital converter (10) is configured for operation in the calibration mode during power-up of the time-interleaved analogue-to-digital converter.
Regarding claim 5, Danson also teaches wherein the time-interleaved analogue-to-digital converter (10) is configured, for a single calibration process, to operate in the calibration mode for a pre-defined time period.
Regarding claim 9, Danson also teaches wherein the time-interleaved analogue-to-digital converter (10) is configured to receive at least one calibration voltage signal (22) at the analogue input.
Regarding claim 13, Danson also teaches a voltage source, arranged to supply the at least one calibration voltage signal (22) to the analogue input of the time-interleaved analogue-to-digital converter (10).
Regarding claim 14, claim 14 is similar to claim 1 in method format. Therefore, claim 14 is rejected as well as rejected in claim 1, such as: a first analogue-to-digital converter (18, ADCa), arranged to sample an analogue input (IN) and produce a digital output (n) based on the sampled analogue Input; a second analogue-to-digital converter (18, ADCb), arranged to sample the analogue input (IN) and produce a digital output (n) based on the sampled analogue input; a signal interleaving portion (20), arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter to produce a digital output signal (Digital Out); the time-interleaved analogue-to-digital converter (10) configured for operation both in an operational mode ("Naturally, the control circuitry may be operable, when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried out by the core sub-ADC units of the set." (para. 0042), and in a compensation mode ("The control circuitry may be operable, when one of the core sub-ADC units of the set is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried out by the other core sub-ADC units of the set." (para. 0043), wherein the time-interleaved analogue-to-digital converter (10) is configured to operate in the compensation mode when the third analogue-to-digital converter is non-functional (NB without loss of generality it can be assumed that ADCc is the core sub-ADC unit that was determined to be defective, in the above-mapped example); wherein, in the operational mode, second analogue-to-digital converter (ADCA) is arranged to sample the analogue input (IN) at a first frequency ("... a rate at which they carry out the core conversion operations when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit.",(para 0043) and the second analogue-to-digital converter (ADCA) is arranged to sample the analogue input at a second frequency (NB it is implicit that all sub-ADCs in D1 operate at the same frequency in a given mode; in this case the first and second frequencies are identical); and wherein, in the calibration (or compensation) mode, the second analogue-to-digital converter (ADCA) is arranged to sample the analogue input at a third frequency ("... a faster rate than a rate at which they carry out the core conversion operations when no said sub-ADC unit of said core sub-ADC units of the set is determined to be a defective sub-ADC unit", (para. 0043) and the second analogue-to- digital converter is arranged to sample the analogue input at a fourth frequency (NB it is implicit that all sub-ADCs in D1 operate at the same frequency in a given mode: in this case the third and fourth frequencies are identical), wherein the third frequency is higher than the first frequency ("a faster rate", (para. 0043), and wherein the fourth frequency is higher than the second frequency (NB since the first and second frequencies are identical and the third and fourth frequencies as well, consequently the fourth frequency is also higher than the second frequency, (para. 0043) (see figure 1 and its descriptions).
Regarding claim 15, Danson also teaches operating the time-interleaved analogue-to-digital converter (10) in the calibration mode during power-up of the time- interleaved analogue-to-digital converter (10).
Claims 1-5, 9 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ragab et al. (US 2016/0149582).
Regarding claim 1, Ragab discloses background calibration of TIADC architecture in figure 3 that teaches: a first analogue-to-digital converter (307), arranged to sample an analogue input periodically and produce a digital output (D1) based on the sampled analogue input; a second analogue-to-digital converter (307), arranged to sample the analogue input periodically and produce a digital output (D2) based on the sampled analogue input; and a signal interleaving portion (309), arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter to produce a digital output signal; the time-interleaved analogue-to-digital converter (300) configured for operation both in an operational mode and in a calibration mode; wherein, in the operational mode, the second analogue-to-digital converter is arranged to sample the analogue input a first time period after the first analogue-to- digital converter samples the analogue input; and wherein, in the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter sampling the analogue input; or wherein, in the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input a second time period apart from a time at which the first analogue-to-digital converter samples the analogue input, wherein the second time period is shorter than the first time period (see figure 3 and its descriptions).
Regarding claim 2, Ragab also teaches wherein in the calibration mode the second analogue-to-digital converter (ADC2) is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter sampling the analogue input.
Regarding claim 3, Ragab also teaches wherein the time-interleaved analogue-to-digital converter (300) is configured for operation in the calibration mode during a period of time in which an expected value of the analogue input is known.
Regarding claim 4, Ragab also teaches wherein the time-interleaved analogue-to-digital converter (300) is configured for operation in the calibration mode during power-up of the time-interleaved analogue-to-digital converter.
Regarding claim 5, Ragab also teaches wherein the time-interleaved analogue-to-digital converter (300) is configured, for a single calibration process, to operate in the calibration mode for a pre-defined time period.
Regarding claim 9, Ragab also teaches wherein the time-interleaved analogue-to-digital converter (300) is configured to receive at least one calibration voltage signal (301) at the analogue input.
Regarding claim 13, Danson also teaches a voltage source, arranged to supply the at least one calibration voltage signal (301) to the analogue input of the time-interleaved analogue-to-digital converter (300).
Regarding claim 14, claim 14 is similar to claim 1 in method format. Therefore, claim 14 is rejected as well as rejected in claim 1, such as: a first analogue-to-digital converter (307), arranged to sample an analogue input periodically and produce a digital output (D1) based on the sampled analogue input; a second analogue-to-digital converter (307), arranged to sample the analogue input periodically and produce a digital output (D2) based on the sampled analogue input; and a signal interleaving portion (309), arranged to combine the digital outputs from the first analogue-to-digital converter and the second analogue-to-digital converter to produce a digital output signal; the time-interleaved analogue-to-digital converter (300) configured for operation both in an operational mode and in a calibration mode; wherein, in the operational mode, the second analogue-to-digital converter is arranged to sample the analogue input a first time period after the first analogue-to- digital converter samples the analogue input; and wherein, in the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter sampling the analogue input; or wherein, in the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input a second time period apart from a time at which the first analogue-to-digital converter samples the analogue input, wherein the second time period is shorter than the first time period (see figure 3 and its descriptions).
Regarding claim 15, Ragab also teaches operating the time-interleaved analogue-to-digital converter (300) in the calibration mode during power-up of the time- interleaved analogue-to-digital converter (300).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: wherein the time-interleaved analogue-to-digital converter is configured to derive respective calibration corrections for the first analogue-to-digital converter and the second analogue-to-digital converter based on the digital outputs of the first analogue-to-digital converter and the second analogue-to-digital converter produced in the calibration mode.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: wherein the time-interleaved analogue-to-digital converter is configured to derive the calibration corrections for each of the analogue-to-digital converters by calculating the adjustment needed to bring the digital outputs of the first and second analogue-to-digital converters into alignment with an expected value of the analogue signal.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: wherein the time-interleaved analogue-to-digital converter is configured to apply the derived respective calibration corrections to the digital outputs of the first analogue-to-digital converter and the second analogue-to-digital converter during operation in the operational mode.
Claim 10 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: wherein the calibration voltage signal comprises a gain-and/or-offset-calibration signal, wherein the gain-and/or-offset-calibration signal has at least two different values, at different times, and wherein the time-interleaved analogue-to-digital converter is configured to derive calibration corrections for gain and/or offset for the first analogue-to-digital converter and the second analogue-to-digital converter based on comparing the digital outputs of the first analogue-to-digital converter and the second analogue-to-digital converter with the corresponding value of the gain-and/or-offset-calibration signal.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: wherein the calibration voltage signal comprises a sloped time-calibration signal, wherein the time-interleaved analogue-to-digital converter is configured to derive a timing correction for the first analogue-to-digital converter and/or the second analogue-to- digital converter based on comparing digital outputs of the first analogue-to-digital converter and the second analogue-to-digital converter, output based on samples of the time-calibration signal taken at different times.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art of record, considered individually or in combination fails to fairly teach or suggest objected features, which is: adjust sample timings at which the first analogue-to-digital converter and/or the second analogue-to-digital converter sample the analogue input based on the derived timing corrections.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/ Primary Examiner, Art Unit 2845
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