DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,211,506. Although the claims at issue are not identical, they are not patentably distinct from each other because following comparison:
Application No. 19/010,972
U.S. Patent No. 12,211,506
Claims 21 and 26-28 correspond to
Claim 1
Claim 22 corresponds to
Claims 2
Claim 23 corresponds to
Claim 3
Claim 24 corresponds to
Claim 4
Claim 25 corresponds to
Claim 5
Claims 29 and 33-35 correspond to
Claim 9
Claim 30 corresponds to
Claim 10
Claim 31 corresponds to
Claim 12
Claim 32 corresponds to
Claim 13
Claim 36 corresponds to
Claim 16
Claims 37-40 correspond to
Claim 17
Allowable Subject Matter
Claims 21-20 would be allowable if the Applicant can overcome the Double Patenting rejection set forth.
The following is a statement of reasons for the indication of allowable subject matter:
Singer et al. (US 2013/0223635) teaches low-power audio detection, signaling a power controller when a predetermined sound is detected, and storing audio for later processing. [0027] states that the detector detects a predetermined audio signal and that its “detection signal 132 may be provided to power controller 112.” [0071] describes storing audio during low-power operation so the awakened device can “determine the exact signal that caused triggering,” while [0076] describes storing “about 1 to 2 seconds of audio signals” for an entire keyword. These teachings are relevant to the claims’ pattern detection, power-management communication, and preservation of triggering audio.
Esliger (US 2009/0292934) teaches an integrated circuit that powers down its CPU and primary memory controller while retaining an always-on secondary memory-controller island. [0037] describes causing the primary controller “to be power gated” and states that the energy controller “may power gate the CPU 113.” During startup, [0039], [Fig. 9], describe sending an instruction to the energy controller “instructing it to wakeup the primary memory controller 104” and polling “to check whether the primary memory controller 104 is active.” These teaching are relevant to the claims’ processor/controller power states, power management communication, and controller readiness condition.
Dahan et al. (US 2007/0130383) teaches buffered audio transfers using a DMA controller and power and clock control module (PCCM). [0040], [Fig. 2], describe transferring “audio information from the microphone to memory storage device 245 using DMA controller 200.” [0043] states that the PCCM “may reduce or eliminate power to DMA controller 200,” and [0045] describes the audio interface sending “a wakeup event to PCCM 100.” These teachings are relevant to the claims’ buffered audio-transfer path and power controlled resumption of transfers.
The difference between the prior art and the claimed invention is that the above prior arts do not explicitly teach continue buffering, in the buffer in the first circuit, subsequently-received audio samples until the memory controller is available to receive writes of audio samples from the buffer to a memory.
Therefore, it would not have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the teachings of the above prior art to include continue buffering, in the buffer in the first circuit, subsequently-received audio samples until the memory controller is available to receive writes of audio samples from the buffer to a memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bertelsen et al. (US 8,024,591) – An integrated circuit comprising a plurality of processing cores, characterized by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.
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SHREYANS A. PATEL
Primary Examiner
Art Unit 2653
/SHREYANS A PATEL/Examiner, Art Unit 2659
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