DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 15-20 in the reply filed on July 20, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Freeman (US 2001/0055427 A1, referred to herein as “Freeman”).
Regarding claim 1, Freeman discloses: A video signal processing method of a video signal processing device, comprising:
decoding a first coding unit of a bitstream in which a video sequence is encoded and generating decoded pixels (Freeman: Fig. 1, paragraph [0019], disclosing that an encoded video bitstream is received and decoded by a variable length code decoder section; paragraph [0021], disclosing that an image data decoding section generates decoded pixel values based on decoded quantized coefficients);
generating at least a part of a current picture frame using the decoded pixels (Freeman: Fig. 1, paragraph [0021], disclosing that decoded pixel values are used to generate a decoded picture); and
storing the current picture frame in a current picture buffer memory that includes a plurality of memory devices (Freeman: paragraph [0023], disclosing storage of pixel data in a frame memory having at least two memory banks),
wherein storing the current picture frame in the current picture buffer memory includes alternately storing the decoded pixels for every certain number of pixels along a row and a column of the current picture frame in different memory devices of the plurality of memory devices as a part of the current picture frame (Freeman: Fig. 2, paragraphs [0023]-[0030], claim 9, disclosing alternately storing rows of pixel blocks—arranged in rows and columns—of an image frame in first and second memory banks, respectively).
Regarding claim 3, Freeman discloses: The video signal processing method of claim 1, wherein each row of the current picture frame includes pixels stored in different memory devices, and each column of the current picture frame includes pixels stored in different memory devices (Freeman: Fig. 2, paragraphs [0012] and [0023]-[0030], claim 9, disclosing alternately storing rows of pixel blocks—arranged in rows and columns—of an image frame in first and second memory banks, respectively).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Zhang et al. (US 2012/0002901 A1, referred to herein as “Zhang”).
Regarding claim 2, Freeman disclose: The video signal processing method of claim 1, further comprising reading at least some pixels located at a same row of the current picture frame from the memory devices… (Freeman: paragraph [0024], disclosing storage of pixels along a same row).
Freeman does not explicitly disclose: for a same clock period of a clock signal.
However, Zhang discloses: for a same clock period of a clock signal (Zhang: paragraph [0064], disclosing reading pixel values in a row during a first clock period).
At the time the application was effectively filed, it would have been obvious for a person having ordinary skill in the art to use the clock period of Zhang when reading pixel data of Freeman.
One would have been motivated to modify Freeman in this manner in order to more quickly process image data (Zhang: paragraph [0036]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Hu et al. (US 2023/0097724 A1, referred to herein as “Hu”).
Regarding claim 6, Freeman discloses: The video signal processing method of claim 1, as discussed above.
Freeman does not disclose: obtaining information about a prediction mode of a second coding unit from the bitstream, wherein the prediction mode is one of an intra string mode or an intra block mode; and decoding the second coding unit based on the current picture frame and the prediction mode.
However, Hu discloses: obtaining information about a prediction mode of a second coding unit from the bitstream (Hu: paragraph [0130], disclosing use of a prediction mode in video coding), wherein the prediction mode is one of an intra string mode or an intra block mode (Hu: paragraph [0077], disclosing intra prediction modes that include an intra prediction mode, an intra block copy mode, and an intra string copy mode); and decoding the second coding unit based on the current picture frame and the prediction mode (Hu: paragraph [0042], disclosing decoding of picture information based on the prediction mode).
At the time the application was effectively filed, it would have been obvious for a person having ordinary skill in the art to use the prediction modes of Hu in the video signal processing method of Freeman.
One would have been motivated to modify Freeman in this manner in order to improve coding efficiency of residual data (Hu: paragraphs [0003] and [0011]).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Zhou et al. (US 2019/0208217 A1, referred to herein as “Zhou”).
Regarding claim 15, Freeman discloses: A video signal processing device (Freeman: Fig. 1, disclosing a coding device), comprising:
a bitstream processing logic that decodes a bitstream in which video data is encoded and generates residual data (Freeman: Fig. 1, paragraphs [0018]-[0022], disclosing a decoder that decodes encoded video and generates residual data);
a reconstructor that generates pixel data reconstructed based on the residual data and intra prediction data (Freeman: Fig. 1, paragraphs [0018]-[0022], disclosing that a combine and interpolate section generates predicted macroblocks of pixels via an intra coding process);
[…]; and
a memory controller that stores the current picture frame in a current picture buffer memory that includes a plurality of memory devices based on the reconstructed pixel data (Freeman: Fig. 1, paragraph [0020], disclosing a frame memory that stores a current picture in a picture buffer; paragraph [0023], disclosing that the memory includes a plurality of memory devices), wherein the memory controller alternately stores decoded pixels for every certain number of pixels along a row and a column of the current picture frame in different memory devices of the plurality of memory devices as a part of the current picture frame (Freeman: Fig. 2, paragraphs [0023]-[0030], claim 9, disclosing alternately storing rows of pixel blocks—arranged in rows and columns—of an image frame in first and second memory banks, respectively).
Freeman does not explicitly disclose: an intra predictor that generates the intra prediction data based on a current picture frame.
However, Zhou discloses: an intra predictor that generates the intra prediction data based on a current picture frame (Zhou: Fig. 4b, paragraph [0075], disclosing an intra predictor that predicts sample values of a current block of the current picture).
At the time the application was effectively filed, it would have been obvious for a person having ordinary skill in the art to use the intra predictor of Zhou in the video signal processing device of Freeman.
One would have been motivated to modify Freeman in this manner in order to improve coding quality associated with intra prediction modes such as intra block copy (Zhou: paragraphs [0002]-[0006]).
Regarding claim 16, Freeman and Zhou disclose: The video signal processing device of claim 15, wherein the plurality of memory devices comprise a plurality of on-chip memory devices (Zhou: paragraphs [0030] and [0142], disclosing on-chip memory devices to store picture information).
The motivation for combining Freeman and Zhou has been discussed in connection with claim 15, above.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman in view of Zhou as applied to claim 15 above, and further in view of Zhang.
Regarding claim 17, Freeman and Zhou disclose: The video signal processing device of claim 15, wherein the memory controller reads at least some pixels located at a same row of the current picture frame from the memory devices (Freeman: paragraph [0024], disclosing storage of pixels along a same row) for a same clock period of a clock signal.
However, Zhang discloses: for a same clock period of a clock signal (Zhang: paragraph [0064], disclosing reading pixel values in a row during a first clock period).
At the time the application was effectively filed, it would have been obvious for a person having ordinary skill in the art to use the clock period of Zhang when reading pixel data of Freeman and Zhou.
One would have been motivated to modify Freeman and Zhou in this manner in order to more quickly process image data (Zhang: paragraph [0036]).
Additional Prior Art References
The following relevant prior art references, not relied upon the rejection above, are made of record.
Wang et al. (US 2022/0224888 A1) discloses storing pixels in a current decoding block using first and second parts of a storage space.
Allowable Subject Matter
Claims 4, 5, 7, 8, 9, 10, 18, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4 and 5, Freeman, either alone or in combination with other prior art of record, does not teach, suggest, or disclose wherein storing the current picture frame in the current picture buffer memory comprises: storing a first pixel group of a plurality of pixel groups in a first memory device of the plurality of memory devices in the current picture frame; and storing pixel groups located at top, bottom, left, and right sides adjacent to the first pixel group in other memory devices of the plurality of memory devices in the current picture frame, wherein the current picture frame includes pixel groups that include MxN pixels, wherein M and the N are each integer numbers equal to or greater than 1.
Regarding claims 7 and 8, Freeman, either alone or in combination with other prior art of record, does not teach, suggest, or disclose, when the prediction mode of the second coding unit is an intra string mode: obtaining, from the bitstream, a first string vector and a first string length of a first sub- string of a plurality of sub-strings of the second coding unit; reading first pixels of the current picture frame that corresponds to the first string length from a position indicated by the first string vector in the current picture frame; and decoding the first sub-string based on the first pixels, wherein at least a part of the first pixels are located on a same row of the current picture frame and are read from different memory devices of the plurality of memory devices.
Regarding claims 9 and 10, Freeman, either alone or in combination with other prior art of record, does not teach, suggest, or disclose, when the prediction mode of the second coding unit is an intra block mode: obtaining, from the bitstream, a first block vector and a first block size of a first block of a plurality of blocks of the second coding unit; reading second pixels of the current picture frame that correspond to the first block size from a position indicated by the first block vector in the current picture frame; reading at least a part of the second pixels from a third pixel group and a fourth pixel group, which are located adjacent to each other along a row of the current picture frame, of a plurality of pixel groups of the current picture frame; and decoding the first block based on the second pixels, wherein the third pixel group and the fourth pixel group are stored in different memory devices of the plurality of memory devices.
Regarding claims 18, 19 and 20, Freeman, either alone or in combination with other prior art of record, does not teach, suggest, or disclose wherein the memory controller stores a first pixel group of a plurality of pixel groups in a first memory device of the plurality of memory devices in the current picture frame, and stores pixel groups located at top, bottom, left, and right sides adjacent to the first pixel group in other memory devices of the plurality of memory devices in the current picture frame, and the current picture frame includes the pixel groups that include MxN pixels, wherein M and the N are each an integer number equal to or greater than 1.
Conclusion
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CHRISTOPHER T. BRANIFF
Primary Examiner
Art Unit 2484
/CHRISTOPHER BRANIFF/Primary Examiner, Art Unit 2484
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