Prosecution Insights
Last updated: July 17, 2026
Application No. 19/011,010

MEMORY DEVICE DECODING USING RELIABILITY VALUES

Non-Final OA §103
Filed
Jan 06, 2025
Priority
Jan 08, 2024 — provisional 63/618,551
Examiner
AHMED, ENAM
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1y 8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
600 granted / 732 resolved
+27.0% vs TC avg
Strong +20% interview lift
Without
With
+20.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
12 currently pending
Career history
741
Total Applications
across all art units

Statute-Specific Performance

§101
8.8%
-31.2% vs TC avg
§103
62.9%
+22.9% vs TC avg
§102
20.6%
-19.4% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 732 resolved cases

Office Action

§103
CTNF 19/011,010 CTNF 83226 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 35 U.S.C. 103 07-20-fti The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made . 07-21 AIA Claim s 1-4, 8-11 and 15-17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kumar et al. (US Pub. No. 2017/0279468) in view of (TORII - US Pub. No. 2007/0277060) . With respect to claim 1 and 8, the Kumar et al. reference teaches detecting a failure to decode a first codeword, the first codeword including user data and first level parity data for the user data([0123] - possible data intersections that can contain errors. Along similar lines, all POP component codewords failing can provide possible data chunks in parity that can have errors); reading a second codeword in response to the detected failure, the second codeword including second level parity data for the user data ([0123] - possible data intersections that can contain errors. Along similar lines, all POP component codewords failing can provide possible data chunks in parity that can have errors)); selecting a first set of one or more reliability values for the second level parity data, the first set of reliability values differing from a second set of reliability values for the user data and the first level parity data ([0052] - Detector 130 performs detection on the received data and outputs decision and/or reliability information corresponding to one or more bits in a codeword.). The Kumar et al. reference does not teach and decoding the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values. The TORII reference teaches and decoding the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values (page 7, line 37 - page line 4 - (1) Error correction of user data + parity # 1 is performed using parity # 1. (2) When error correction of (1) fails, error correction of user data + parity # 1 + parity # 2 is performed using parity # 1 to parity # 2. (3) When error correction of (2) fails, error correction of user data + parity # 1 + parity # 2 + parity # 3 is performed using parity # 1 to parity # 3. ... (N) When error correction of (n−1) fails, error correction of user data + parity # 1 + parity # 2 + parity # 3 +... + Parity #n is performed using parity # 1 to parity #n). Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Kumar et al.. and TORII to incorporate teach and decoding the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values into the claimed invention. The motivation for and decoding the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values. is for improved reliability (page 10, line 57 – page 11, line 1 - TORII). With respect to claims 2 and 9, the Kumar et al. reference teaches decoding the second codeword, wherein selecting the first set of one or more reliability values uses a result of decoding the second decoding the second codeword, wherein selecting the first set of one or more reliability values uses a result of decoding the second codeword ([0085 – At 730 , the decoder determines if the received LLR value is equal to or less than the target threshold value. If yes, the decoder determines that the corresponding bit is a good candidate for “least reliable bits). With respect to claims 3, 10 and 16, the Kumar et al. reference teaches selecting the first set of one or more reliability values as a maximum reliability value in response to successfully decoding the second codeword ([0099] - a more lenient threshold (e.g., a higher value of threshold can be used in the decoding). As an example, a bit in error having an LLR value equal to 1.4, with an initial threshold equal to one, will not get flipped until the threshold is increased with iterations and becomes greater than 1.4. In one example, a lower threshold value (e.g., one) may be used at the beginning of decoding and a higher threshold value (e.g., 1.5) can be used after four decoding iterations.). With respect to claims 4, 11 and 17, the Kumar et al. reference teaches further comprising: freezing the second codeword to prevent bits of the second codeword from changing during the decoding of the user data in response to successfully decoding the second codeword ([0085] - the decoder may want to select 10 least reliable bits. As soon as the decoder finds the 10 th bit, the decoder may stop the process of least reliable bit selection (e.g., at 760 ) and move to the next step of the TPC decoding process (e.g., the bit flipping process). With respect to claim 15, the Kumar et al. reference teaches a plurality of memory devices ([0019] - memory array); and a processing device, operatively coupled with the plurality of memory devices, to: detect a failure to decode a first codeword, the first codeword including user data and first level parity data for the user data ([0123] - possible data intersections that can contain errors. Along similar lines, all POP component codewords failing can provide possible data chunks in parity that can have errors); read a second codeword in response to the detected failure, the second codeword including second level parity data for the user data ([0123] - possible data intersections that can contain errors. Along similar lines, all POP component codewords failing can provide possible data chunks in parity that can have errors)); decode the second codeword ([0123] - possible data intersections that can contain errors. Along similar lines, all POP component codewords failing can provide possible data chunks in parity that can have errors); select a first set of one or more reliability values for the second level parity data using a result of decoding the second codeword, the first set of reliability values differing from a second set of reliability values for the user data and the first level parity data ([0052] - Detector 130 performs detection on the received data and outputs decision and/or reliability information corresponding to one or more bits in a codeword.). The Kumar et al. reference does not teach and decode the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values.. The TORII reference teaches and decode the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values (page 7, line 37 - page line 4 - (1) Error correction of user data + parity # 1 is performed using parity # 1. (2) When error correction of (1) fails, error correction of user data + parity # 1 + parity # 2 is performed using parity # 1 to parity # 2. (3) When error correction of (2) fails, error correction of user data + parity # 1 + parity # 2 + parity # 3 is performed using parity # 1 to parity # 3. ... (N) When error correction of (n−1) fails, error correction of user data + parity # 1 + parity # 2 + parity # 3 +... + Parity #n is performed using parity # 1 to parity #n). Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Kumar et al.. and TORII to incorporate teach and decode the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values into the claimed invention. The motivation for and decode the user data using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values is for improved reliability (page 10, line 57 – page 11, line 1 - TORII). Allowability 12-151-08 AIA 07-43 12-51-08 Claim 5-7, 12-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-101 Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729 . The examiner can normally be reached on Mon-Fri from 8:30 A.M . to 5:30 P.M . If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady , can be reached on 571-272-3819 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). EA 6/5/26 /ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112 Application/Control Number: 19/011,010 Page 2 Art Unit: 2112 Application/Control Number: 19/011,010 Page 3 Art Unit: 2112 Application/Control Number: 19/011,010 Page 4 Art Unit: 2112 Application/Control Number: 19/011,010 Page 5 Art Unit: 2112 Application/Control Number: 19/011,010 Page 6 Art Unit: 2112 Application/Control Number: 19/011,010 Page 7 Art Unit: 2112
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Prosecution Timeline

Jan 06, 2025
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+20.0%)
3y 2m (~1y 8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 732 resolved cases by this examiner. Grant probability derived from career allowance rate.

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