DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 01/06/25. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2,4-6, 11-12, 14-16, 19-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun (US 11081953 B2)
Regarding claim 1. Sun teaches a circuit [figs 4, coupled is interpreted as connected between intervening elements] comprising: a boost converter [boost of fig 4] including an input [vin] configured to couple to a source input, boost circuitry configured to generate an output power [see LX] with a higher voltage than a voltage of the source input, an output [vout] configured to deliver the output power, at least one capacitor [cout] coupled between the boost output and ground, and a feedback [Vfb] and control circuit configured to sense an output voltage of the output power and regulate the output voltage to a predefined level [see CP1];
a power disconnect switch [Q2] including a first terminal [source terminal] arranged to receive the output power and a second terminal [drain terminal] configured to couple to a load;
a comparator [CP3] including a first input terminal configured to couple to the source input, a second input terminal coupled to the output, and a first output terminal configured to output a condition signal [V1] indicating a condition of the output voltage being less than or equal to the voltage of the source input [implicit from item in 402]; and
a control circuit [402 w/ inverter logic gate] including an input terminal [input of inverter logic gate] coupled to the first output terminal of the comparator and a second output terminal [see Vg] coupled to the power disconnect switch, the control circuit being configured to open the power disconnect switch in response to receiving the condition signal indicating the condition.
Regarding claim 2. Sun teaches the circuit of claim 1, wherein the control circuit is configured to close the power disconnect switch in response to the output voltage becoming higher than the input voltage by a predefined amount [figure 6 shows power switch being on will Vout is greater than Vin].
Regarding claim 4. Sun teaches the circuit of claim 1, wherein the control circuit further includes logic configured to close the power disconnect switch after a delay [delay from inverter logic of circuit 401].
Regarding claim 5. Sun teaches the circuit of claim 1, wherein the control circuit further includes logic [function of RS] configured to shut down the boost converter and keep the disconnect switch open until after a reset.
Regarding claim 6. Sun teaches the circuit of claim 1, further comprising at least one voltage offset [ground offset added with Cin] added to at least one of the first input terminal of the comparator and the second input terminal of the comparator, wherein the condition indicates the output voltage is less than or equal to the voltage of the source input plus the offset [function of CP 3].
Regarding claim 11. Sun teaches a circuit [figs 4, coupled is interpreted as connected between intervening elements] comprising: a power disconnect switch [Q2] including a first terminal [source terminal] configured to couple to a boost converter [boost of figure 4] output and a second terminal [drain terminal] configured to couple to a load [load intended for boost circuit];
a comparator [CP3] including a first input terminal configured to couple to a source input, a second input terminal configured to couple to the boost converter output, and a first output terminal configured to output a signal indicating a condition [V1] of the boost converter output being less than or equal to the source input;
and a control circuit [402 with inverter logic gate] including an input terminal [input of inverter logic gate] coupled to the first output terminal of the comparator and a second output terminal [See Vg] coupled to the power disconnect switch, the control circuit being configured to open the power disconnect switch in response to receiving the signal indicating the condition.
Regarding claim 12. Sun teaches the circuit of claim 11, wherein the control circuit is configured to close the power disconnect switch in response to the output voltage becoming higher than the input voltage by a predefined amount [figure 6 shows power switch being on will Vout is greater than Vin].
Regarding claim 14. Sun teaches the circuit of claim 11, wherein the control circuit further includes logic configured to close the power disconnect switch after a delay [delay from inverter logic of circuit 401].
Regarding claim 15. Sun teaches the circuit of claim 11, wherein the control circuit further includes logic [function of RS] configured to shut down the boost converter and keep the disconnect switch open until after a reset.
Regarding claim 16. Sun teaches the circuit of claim 11, further comprising at least one voltage offset added [ground offset added with cin] to at least one of the first input terminal of the comparator and the second input terminal of the comparator, wherein the condition indicates the output voltage is less than or equal to the voltage of the source input plus the offset [function of CP 3].
Regarding method claims 19-20, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 11081953 B2) in view of Bucheru (US 10742125 B1 and hereinafter as Ben)
Regarding claim 10. Sun teaches the circuit of claim 1, the boost converter [fig 4].
However, Sun teaches a circuit wherein the converter further includes a valley current control circuit configured to reduce a switching frequency in response to an inductor current of the boost converter exceeding a predefined threshold.
Bucheru teaches wherein the converter further includes a valley current control circuit configured to reduce a switching frequency in response to an inductor current of the converter exceeding a predefined threshold [col 5 lines 5-20].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Bucheru in order to provide reduce effective switching frequency, so the MOSFETs switches fewer times and waste less energy and also fewer switching events means lesser thermal and electrical stress on the MOSFET.
Allowable Subject Matter
Claims 3,7-9,13 and 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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