DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/011,067 filed on 1/6/2025.
Claims 1-25 have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/6/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
Claims 1, 10, and 11, are method claims that include one or more contingent clauses, such as “doing X, based at least in part on Y” and do not explicitly claim that the condition, Y, positively occurs in the claimed language. The broadest reasonable interpretation of these claims does not include those X steps occurring. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04 (II).
Looking at claim 1, for example, the claim states, “adjusting a counter by a first value based at least in part on the temperature satisfying a first threshold,” and “performing one or more protection operations…based at least in part on the counter satisfying a second threshold.” But the claim never explicitly recites that the temperature satisfies the first threshold or that the counter satisfies the second threshold. As a result, the broadest reasonable interpretation of these limitations are that the temperature and the counters do not satisfy their respective thresholds and therefore, the adjusting the counter and performing one or more protection operations does not need to occur in the prior art for the claim to be met by the prior art. Claims 10 and 11 also claim similar contingent limitations without positively reciting that their condition occurs in the claim language and therefore have a similar interpretation.
Claims 1, 5-9, 12-13 each contain limitations that further define the, limitations in question above. Since the broadest reasonable interpretation of each claim is that these limitations are contingent and as written do not need to occur, the further defining limitations from claims 1, 5-9, 12-13 also do not need to occur in the prior art in order for the prior art to meet the limitations of each respective claim as they merely further define something that is not required to occur within the claim.
The examiner encourages the applicant to positively recite these conditions occurring in the claim limitations so that the resulting steps would be required to occur under the broadest reasonable interpretation of each claim. As an example for claim 1, “determine that the temperature satisfies a first threshold; determine that a counter satisfies a second threshold; adjusting the counter by a first value based at least in part on the temperature satisfying the first threshold; and performing one or more protection operations on one or more blocks of memory cells of the memory system based at least in part on the counter satisfying the second threshold,”
The examiner would like to note, that in the interest of compact prosecution, prior art is being applied to claims 1, 5-13, as if the claims positively recited the limitations in question.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4, 10-11, 14-17, 19, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US 2021/0216216) and Nakano et al. (US 2021/0303214).
With respect to claim 1, Brandt teaches of a method by a memory system, comprising: monitoring a temperature associated with the memory system (fig. 4; paragraph 50; where the processing device receives temperature measurements from the memory devices);
adjusting a counter by a first value based at least in part on the temperature satisfying a first threshold (fig. 4; paragraph 53-54; where if a temperature differs from the average temperature by at least a difference temperature threshold, it is an outlier temperature and the count of outlier temperatures is increased); and
performing one or more protection operations on one or more blocks of memory cells of the memory system based at least in part on the counter satisfying a second threshold (fig. 4; paragraph 53-60; when the count of outlier temperatures measurements is greater than the distribution threshold, the cross temperature error correction priority is increased when it is not already at the maximum priority).
Brandt fails to explicitly teach of the one or more protection operations comprising programming a respective data pattern to each of the one or more blocks of memory cells.
However, Nakano teaches of the one or more protection operations comprising programming a respective data pattern to each of the one or more blocks of memory cells (fig. 19-20; paragraph 100-101; where when data is written the ECC (claimed data pattern) is generated from the data and written in the frame with the data. In the combination with Brandt, this ECC writing occurs in response to which cross temperature error correction scheme has the priority).
Brandt and Nakano are analogous art because they are from the same field of endeavor, as they are directed to managing memory systems.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt and Nakano before the time of the effective filing of the claimed invention to incorporate the writing of the error correction schemes to memory when writing data to the memory in Brandt as taught in Nakano. Their motivation would have been to efficiently check and correct for bit errors in the data (Nakano, paragraph 43).
With respect to claim 16, the combination of Brandt and Nakano teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Brandt also teaches of a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to perform the method of claim 1 (fig. 1, 5; paragraph 23, 63; where the memory subsystem controller communicates with the memory devices to perform the disclosed operations).
With respect to claim 25, the combination of Brandt and Nakano teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Brandt also teaches of a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (fig. 1, 5; paragraph 23, 63, 67-68; where a machine readable medium stores software that is executed by the processing device to perform the disclosed operations).
With respect to claims 2 and 17, Brandt teaches of wherein monitoring the temperature comprises: performing a plurality of temperature measurements of the memory system over a duration; and determining an average temperature for the duration based at least in part on the plurality of temperature measurements, wherein the temperature comprises the average temperature (fig. 4; paragraph 50-51; where operating temperature measurements are periodically received and stored and every trigger event (amount of time passing or number of PE cycles) causes an average temperature to be calculated).
With respect to claim 4 and 19, Brandt teaches of modifying the duration over which measurements are taken, wherein performing the plurality of temperature measurements is based at least in part on modifying the duration (paragraph 50-51; where the media temperature manager uses any amount of time passing to trigger the calculation of an average temperature).
With respect to claim 10, Brandt teaches of monitoring a second temperature associated with the memory system; and adjusting the counter by a second value greater than the first value based at least in part on the second temperature satisfying a third threshold greater than the first threshold, wherein performing the one or more protection operations is based at least in part on adjusting the counter by the second value (fig. 3, paragraph 42-43, 46, claims 3, 5; where the higher dynamic threshold is increased again in response to the average temperature being satisfying the higher dynamic threshold).
With respect to claim 11, Brandt teaches of monitoring a second temperature of a block of the one or more blocks of memory cells; adjusting a second counter based at least in part on the second temperature satisfying a third threshold; and performing one or more second protection operations on the block based at least in part on the second counter satisfying a fourth threshold (fig. 4; paragraph 50, 53-60; where the system includes multiple memory subsystems that carry out the invention. Therefore, it also occurs in the other memory subsystems).
With respect to claim 14, Brandt teaches of modifying a parameter corresponding to the first threshold, wherein adjusting the counter is based at least in part on modifying the parameter (paragraph 51, 53-54; where the average temperature is determined every ‘an amount of time passing’. The threshold is the values that are the threshold deviation away from the average temperature, thus updating the average temperature changes the values of the threshold that determines an outlier temp value that updates the count of outlier temp values).
With respect to claim 15, Brandt teaches of modifying a parameter corresponding to the second threshold, wherein performing the one or more protection operations is based at least in part on modifying the parameter (paragraph 54; where a count of the outlier temperature values is tracked. The counting of the outlier temperature values is the claimed modifying a parameter corresponding to the distribution threshold, since it is compared to the distribution threshold to determine if it is greater than it).
Claim(s) 3 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt and Nakano as applied to claims 2 and 17 above, and further in view of Babitch et al. (US 2010/0250129).
With respect to claims 3 and 18, the combination of Brandt and Nakano fails to explicitly teach of modifying a quantity of the plurality of temperature measurements made in the duration, wherein performing the plurality of temperature measurements is based at least in part on modifying the quantity.
However, Babitch teaches of modifying a quantity of the plurality of temperature measurements made in the duration (paragraph 41; where the measurement rate of the temperature sensor is changed).
The combination of Brandt, Nakano, and Babitch teaches of wherein performing the plurality of temperature measurements is based at least in part on modifying the quantity (Brandt, paragraph 50; Babitch, paragraph 41; where in the combination, the measurement rate of the temperature sensors in the combination of Brandt and Nanako are changed as taught in Babitch).
Brandt, Nakano, and Babitch are analogous art because they are from the same field of endeavor, as they are involve temperature sensing.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, and Babitch before the time of the effective filing of the claimed invention to incorporate the changing the rate of measurement of the temperature sensor in the combination of Brandt and Nakano as taught in Babitch. Their motivation would have been to reduce power consumption (Babitch, paragraph 31).
Claim(s) 5-7, 9, 20-22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt and Nakano as applied to claims 1 and 16 above, and further in view of Hyun et al. (US 2016/0118111).
With respect to claims 5 and 20, the combination of Brandt and Nakano fails to explicitly teach of wherein performing the one or more protection operations comprises: performing a first type of protection operation on one or more erased blocks of the one or more blocks of memory cells; performing a second type of protection operation on one or more partially filled blocks of the one or more blocks of memory cells; and performing a third type of protection operation on one or more open blocks of the one or more blocks of memory cells.
However, Hyun teaches of wherein performing the one or more protection operations comprises: performing a first type of protection operation on one or more erased blocks of the one or more blocks of memory cells (paragraph 121-123; where the first and second pages of an erased block of memory is programmed with workload/user data and a predefined endurance data pattern is programmed to the third page of the erased block);
performing a second type of protection operation on one or more partially filled blocks of the one or more blocks of memory cells (paragraph 121-123; as the first and second pages of the erase block are programmed and the unused/unavailable their page of the erased block is programmed with a predefined endurance data pattern); and
performing a third type of protection operation on one or more open blocks of the one or more blocks of memory cells (fig. 13; paragraph 246-247; where in the RLC mode the first/lower page and a second/middle page of the block are being programmed, this suggests the block is open. The third/upper page is programmed with a predefined endurance data pattern).
Brandt, Nakano, and Hyun are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, and Hyun before the time of the effective filing of the claimed invention to incorporate the programming an endurance pattern to unavailable/unused pages in the combination of Brandt and Nakano as taught in Hyun. Their motivation would have been to continue to reliably use the effected memory blocks as they age and deteriorate (Hyun, paragraph 121).
With respect to claims 6 and 21, Hyun teaches of wherein the second type of protection operation comprises: writing a data pattern to one or more unprogrammed pages of the one or more partially filled blocks (paragraph 121-123; where a predefined endurance data pattern is programmed to the third page as it is an unavailable/unused page in a block with two pages of workload/user data).
The reasoning for obviousness is the same as indicated above with respect to claims 5 and 20.
With respect to claims 7 and 22, Hyun teaches of wherein the second type of protection operation further comprises: refraining from writing the data pattern to one or more programmed pages of the one or more partially filled blocks (paragraph 121-123; where the predefined endurance pattern is programmed to unavailable, restricted pages. It isn’t programmed to available, unrestricted pages).
The reasoning for obviousness is the same as indicated above with respect to claims 5 and 20.
With respect to claims 9 and 24, the combination of Brandt and Nakano fails to explicitly teach of wherein programming a respective data pattern comprises: programming a first voltage to a memory cell of the one or more blocks of memory cells, wherein the first voltage is different than a second voltage corresponding to a first logic state of the memory cell and the first voltage is different than a third voltage corresponding to a second logic state of the memory cell.
However, Hyun teaches of wherein programming a respective data pattern comprises: programming a first voltage to a memory cell of the one or more blocks of memory cells, wherein the first voltage is different than a second voltage corresponding to a first logic state of the memory cell and the first voltage is different than a third voltage corresponding to a second logic state of the memory cell (paragraph 115; where write operations are implemented using multiple stages where each stage includes an incremental voltage level change to programming the memory cell to change the cell from the erase/L0 state to the L1 state).
Brandt, Nakano, and Hyun are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, and Hyun before the time of the effective filing of the claimed invention to incorporate the incremental programming in the combination of Brandt and Nakano as taught in Hyun. Their motivation would have been to more efficiently use the memory.
Claim(s) 8 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt, Nakano, and Hyun as applied to claims 6 and 21 above, and further in view of Gaertner et al. (2014/0241033).
With respect to claims 8 and 23, the combination of Brandt, Nakano, and Hyun fails to explicitly teach of wherein the second type of protection operation further comprises: concurrently activating a plurality of word lines corresponding to the one or more unprogrammed pages.
However, Gaertner teaches of wherein the second type of protection operation further comprises: concurrently activating a plurality of word lines corresponding to the one or more unprogrammed pages (fig. paragraph 19-20; where multiple cells, sectors, pages, blocks, and garbage collection units can be concurrently controlled for read and writing data. In the combination with Brandt, Nakano, and Hyun this includes the programming of the predefined endurance pattern).
Brandt, Nakano, Hyun, and Gaertner are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, Hyun, and Gaertner before the time of the effective filing of the claimed invention to include the concurrent accessing of the memory pages in the combination of Brandt and Nakano and Hyun as taught in Gaertner. Their motivation would have been to more quickly operate the memory.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt and Nakano as applied to claim 1 above, and further in view of Igahara et al. (2018/0211708).
With respect to claim 12, the combination of Brandt and Nakano fails to explicitly teach of storing a value of the counter to a non-volatile portion of the memory system based at least in part on adjusting the counter; and performing a power cycle operation after storing the value of the counter.
However, Igahara teaches of storing a value of the counter to a non-volatile portion of the memory system based at least in part on adjusting the counter; and performing a power cycle operation after storing the value of the counter (paragraph 184; where the counter value is stored in NAND flash memory before power off).
Brandt, Nakano, and Igahara are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, and Igahara before the time of the effective filing of the claimed invention to incorporate the storing the counters of the combination of Brandt and Nakano in NAND flash as taught in Igahara. Their motivation would have been to ensure the data is retained when the power off occurs (Igahara, paragraph 184).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandt and Nakano as applied to claim 1 above, and further in view of Hikimura et al. (2016/0259575).
With respect to claim 13, the combination of Brandt and Nakano fails to explicitly teach of resetting the counter based at least in part on performing the one or more protection operations.
However, Hikimura teaches of resetting the counter based at least in part on performing the one or more protection operations (fig. 6; paragraph 75-76, 82-89; where once the control operation based on gradient have been performed and the memory temperature no longer exceeds the first threshold and returns to original memory control operation, the counter is reset at S7).
Brandt, Nakano, and Hikimura are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Brandt, Nakano, and Hikimura before the time of the effective filing of the claimed invention to incorporate the resetting of the counter in the combination of Brandt and Nakano as taught in Hikimura. Their motivation would have been to rest back to original operation once the need for the temperature management is no more.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chinnakkonda Vidyapoornachary et al. (US 2017/0004040) discloses dynamically adjusting the ECC signature in a memory based on the temperature of the device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138