DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to preliminary amendment filed on 01/06/2025. In this amendment, claims 21-30 were canceled. Claims 1-20 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDSs) were submitted on 08/14/2025 and 01/06/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over applicant provided prior art (APPA) Hatula et al. US 2013/0097390 (“Hatula”) in view of APPA Bamdhamravuri US 2022/0129201 (“Bamdhamravuri”).
As per independent claim 1, Hatula teaches A memory module (memory controller 100 and shared RAM 150-154, Figure 1. “These processes or subsystems may be part of a system (e.g. a system-on-a-chip (SoC))” para 0003) comprising:
a first synchronization control circuit (write port 1, 110, Figure 1, which synchronizes the address signals A1-A4, A1’, the data signals D1-D4 and the write activation signal WREN/PWREN(0) on single clock signal, Figure 4. “the clock signals of each write port 110-112 and the clock signal of the write arbiter 120 may have substantially the same clock frequency”, para 0185) configured to store a first write activation signal (WrEn, which is output as pWrEn(0), Figures 4 and 7. “The write port may also receive from subsystem 160 a write enable signal ‘WrEn’, which indicates whether data is to be written into the write port during any given clock cycle” para 0094), a first write address signal (A1’ on pWriteAddress(0), stored in the write address 216, Figure 4. “the output of the write address buffer 216 is indicated by the signal ‘pWriteAddress(0)’” para 0098), and a first write data signal (D1-D4 in pWriteData(0) stored in the write buffer 214, Figure 4. “In FIG. 4, the output of the write buffer 214 is indicated by the signal ‘pWriteData(0)’” para 0098);
a second synchronization control circuit (write port 2, Figure 1. “each write port 110-112 of the memory controller 100 includes … a write buffer 214, 224, a write address buffer 216, 226, …. The general operation of these components will now be summarized in terms of one of the write ports 110” para 0075) configured to store a second write activation signal (pWrEn(1), Figure 7), a second write address signal (pWriteAddress(1), Figure 7), and a second write data signal (pWriteData(1), Figure 7) (“Also in clock cycle 6 of FIG. 7, the output of write buffer 224 of the second write port 112, indicated by the signal ‘pWriteData(1)’ is set to data D5-D8. Additionally, the output of the write address buffer 226 of the second write port 112, indicated by signal ‘pWriteAddress(1)’ is set to address A2’, and the write enable signal of the write port 112 is raised high” para 0118);
a third synchronization control circuit (“In accordance with another aspect of the present invention, there is provided a memory controller providing a plurality of write ports”, para 0016. “The first write bandwidth requirement may be satisfied by selecting M>=N for a given write port, and the second may be satisfied by selecting M>=p*N, where p is the number of write ports” para 0185. ”It will also be appreciated that, as well as the factors above, the number of write ports 110-112 is another factor that may be selected to ensure that one or more of the write bandwidth requirements may be satisfied” para 0189. “A memory controller providing a plurality of write ports” see claim 1. There is a preponderance of evidence that the invention contemplates more than 2 ports) configured to store a third write activation signal (would be pWrEn(2)) , a third write address signal (would be pWriteAddress(2)), and a third write data signal (would be pWriteData(2));
a fixed priority module (write arbiter 120, Figure 1 and para 0040) configured to:
output a write activation signal (write activation signal on pWrEn(0), pWrEn(1), or pWrEn(2), Figure 4) received from the first synchronization control circuit (write port 1, 110, Figure 1), the second synchronization control circuit (write port 2, 112, Figure 1), or the third synchronization control circuit (third write port) as a register write activation signal (WrX of Figure 6) (the port having the highest priority is selected to provide the write activation signal. “As indicated by the scheduler(0) signal, in clock cycle 6 of Figure 6, the first write port 110 has highest priority.” Para 0121),
output a write address signal (address on pWriteAddress(0), pWriteAddress(1), or pWriteAddress(2), Figures 4 and 7) received from the first synchronization control circuit (write port 1, 110, Figure 1), the second synchronization control circuit (write port 2, 112, Figure 1), or the third synchronization control circuit (third write port) as a register write address signal (WrAddress of Figure 6),
output a write data signal (data on pWriteData(0), pWriteData(1), or pWriteData(2), see Figures 4 and 7) received from the first synchronization control circuit (write port 1, 110, Figure 1), the second synchronization control circuit (write port 2, 112, Figure 1), or the third synchronization control circuit (third write port) as a register write data signal (Data(63:0), Figure 6).
Hatula does not explicitly teach “register write” signals.
However, in an analogous art in the same field of endeavor, Bamdhamravuri teaches register write (“Upon selecting a register access operation, arbitration circuit 127 can forward the corresponding register address information, register data information, and a corresponding write pulse 232 to the one or more command buffer registers 230.” Para 0023 and FIG. 2).
Given the teaching of Bamdhamravuri, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Hatula with “register write” signals. The motivation would be that the invention allows for register writes across clock domains, para 0112 of Bamdhamravuri.
As per dependent claim 6, Hatula in combination with Bamdhamravuri discloses the device of claim 1. Hatula teaches wherein each of the first synchronization control circuit (write port 1, 110, Figure 1), the second synchronization control circuit (write port 2, 112, Figure 1), and the third synchronization control circuit (third write port) comprises: a state controller (controller checking whether the FIFO is full and receiving WrEn as disclosed by Figure 4) configured to receive a corresponding interface write activation signal (WrEn, Figure 4), and to output an interface transmission signal (FIFO Full, para 0098) based on receiving an interface response signal (cmdBuff(3:0) being 1111, Figure 4);
a synchronizer (circuit generating cmdBuff(3:0) and pWrEn(0), para 0097-0098) configured to receive the interface transmission signal (FIFO Full, para 0098), and to output an interface register write activation signal (pWREn(0), Figure 7) and the interface response signal (cmdBuff(3:0), para 0098) by synchronizing the write activation signal (pWREn(0), Figure 7) (“In clock cycle 6, after data has been written into each storage location of the data buffer, all the bits of cmdBuff(3:0) are raised high, indicating that the data buffer is full … once data D1-D4 have been written to the data buffer 210 the write port determines that the data buffer 210 is full, and thus the flush signal ‘FIFO Full’ is raised, i.e., step 310. Additionally data D1-D4 is flushed to the write buffer 214, and address A1’ is flushed to the write address buffer 216 … A write enable signal ‘pWrEn(0)’ is also provided by the write port 110 when the write buffer 214 contains data that is ready to be written to the shared RAM 150 by the write arbiter 120” para 0098).
Allowable Subject Matter
Claims 2-5 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of claim 2 “wherein the first synchronization control circuit corresponds to an eFuse interface” in combination with the overall claimed limitations when interpreted in light of the specification.
Both Hatula and Bamdhamravuri are silent about an e-Fuse. An additional reference Miller et al. US 2015/0019803 (“Miller”) was considered. Miller teaches “a memory BISR (MBISR) [Memory Built-In Self-Repair] engine 370 having an eFUSE block 372 disposed therein.” Para 0088. However, Miller does not teach or suggest “wherein the first synchronization control circuit corresponds to an eFuse interface”. Therefore, claim 2 is an allowable dependent claim.
Claims 3-5 directly or indirectly depend from claim 2 and these claims are allowable by virtue of their dependency to claim 2.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of claim 7 “wherein the fixed priority module comprises: a first logic circuit configured to: execute a first OR operation on one from among a first register write activation signal corresponding to the first synchronization control circuit, a second register write activation signal corresponding to the second synchronization control circuit, and a third register write activation signal corresponding to the third synchronization control circuit, and output a result of the first OR operation as the register write activation signal; a second logic circuit configured to receive a first interface busy signal from the first synchronization control circuit, and to output the received first interface busy signal to the second synchronization control circuit; and a third logic circuit configured to execute a second OR operation on the first interface busy signal and a second interface busy signal received from the second synchronization control circuit, and to output a result of the second OR operation to the third synchronization control circuit” in combination with the overall claimed limitations when interpreted in light of the specification.
Hatula, Bamdhamravuri, and Miller, alone or in any combination, do not teach the subject matter of claim 7 with such specificity. Therefore, claim 7 is an allowable dependent claim.
Dependent claims 8-10 directly or indirectly depend from claim 7 and these claims are also allowable by virtue of their dependency to claim 7.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of independent claim 11 “receiving a first register write command from an eFuse controller” in combination with the overall claimed limitations when interpreted in light of the specification.
Hatula, Bamdhamravuri, and Miller, alone or in any combination, do not teach the subject matter of claim 11 with such specificity. The references are silent about an eFuse controller. Therefore, claim 11 is allowable.
Claims 12-15 directly or indirectly depend from independent claim 11 and these claims are allowable by virtue of their dependency to claim 11.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of independent claim 16 “receiving a first register write command corresponding to an eFuse controller” in combination with the overall claimed limitations when interpreted in light of the specification.
Hatula, Bamdhamravuri, and Miller, alone or in any combination, do not teach the subject matter of claim 11 with such specificity. The references are silent about an eFuse controller. Therefore, claim 11 is allowable.
Claims 17-20 directly or indirectly depend from independent claim 16 and these claims are allowable by virtue of their dependency to claim 16.
It is noted that claims 11 and 16 have the same scope except for the language “from” and “corresponding to”. The Examiner notes that one claim is slightly broader than the other and that is a choice made by the Applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132