Prosecution Insights
Last updated: October 01, 2026
Application No. 19/011,283

SYSTEMS AND METHODS TO REDUCE THE DC LINK CAPACITANCE AND IMPROVE THE RELIABILITY OF CONVERTERS

Non-Final OA §102§103§112
Filed
Jan 06, 2025
Priority
Jan 05, 2024 — provisional 63/618,197
Examiner
TORRES-RIVERA, ALEX
Art Unit
Tech Center
Assignee
Board of Regents of the University of Texas System
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
681 granted / 786 resolved
+26.6% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
809
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This action is in response to the 08/17/2026 Response to Election/Restriction. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Election/Restrictions Claims 10 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/17/2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites “wherein the switches are silicon controlled rectifiers”. However, preceding claim 3 recites “one or more switches of the three different phase modules” and preceding claim 6 recites “wherein one or more of the three different phase modules includes a modified phase module having a combination of fast acting fuses and switches”. I tis unclear in claim 7 if the silicon controlled rectifiers corresponds to the “one or more switches of the three different phase modules” of claim 3 or “the switches” of the modified phase module. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 2 and 9 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2018/0337590; (hereinafter He). Regarding claim 1, He [e.g. Figs. 1 – 3] discloses a three phase Neutral Point Clamped (NPC) converter, comprising: three different phase modules [e.g. three modules having 48, 52 in fault tolerant inverter 12]; at least one redundant phase module [e.g. 16]; and switching circuitry [e.g. 50, 56] configured to enable one of the at least one redundant phase modules in response to failure of one of the three different phase modules [e.g. paragraph 033 recites “FIG. 2 is a schematic diagram that depicts current flow 66 in an embodiment of the fault tolerant T-Type NPC inverter during an exemplary open circuit fault in Switch Sa1. Once an open-circuit fault in IGBT Sa1 occurs, the Phase-A leg of the T-Type inverter will not be able to produce a positive voltage. This fault is exemplarily identified by the microcontroller 26, and the microcontroller 26 provides a control signal through the gate driver circuit 32 to close the positive redundant switch 54 and to close bi-directional midpoint switch 50 (Sa2, Sa3). In such operation, IGBT Sa1 (now with an open fault) is operationally replaced by positive redundant switch 54 (S1) from the redundant phase leg 16 and midpoint switch 50 (Sa2, Sa3)”]. Regarding claim 2, He [e.g. Figs. 1 – 3] discloses further comprising a controller [e.g. 26, 32] that is configured to replace a failed one of the three different phase modules with the one of the at least one redundant phase by operating the switching circuitry [e.g. paragraph 033 recites ““FIG. 2 is a schematic diagram that depicts current flow 66 in an embodiment of the fault tolerant T-Type NPC inverter during an exemplary open circuit fault in Switch Sa1. Once an open-circuit fault in IGBT Sa1 occurs, the Phase-A leg of the T-Type inverter will not be able to produce a positive voltage. This fault is exemplarily identified by the microcontroller 26, and the microcontroller 26 provides a control signal through the gate driver circuit 32 to close the positive redundant switch 54 and to close bi-directional midpoint switch 50 (Sa2, Sa3). In such operation, IGBT Sa1 (now with an open fault) is operationally replaced by positive redundant switch 54 (S1) from the redundant phase leg 16 and midpoint switch 50 (Sa2, Sa3)”]. Regarding claim 9, He [e.g. Figs. 1 – 3] discloses comprising a single redundant phase [e.g. 16]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3 – 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over He in view of US Pub. No. 2025/0379527; (hereinafter Maeda). Regarding claim 3, He [e.g. Figs. 1 – 3] discloses wherein the controller is further configured to electronically remove ripple in an output of the converter by controlling one or more switches of the three different phase modules. Maeda teaches wherein the controller [e.g. 50] is further configured to electronically remove ripple in an output of the converter [e.g. 100] by controlling one or more switches of the three different phase modules [e.g. paragraph 0126 recites “The power converter 100 according to the third embodiment may reduce the chances of causing ripples in the output current while performing the second and third control operations compared to the power converter 100 according to the first embodiment”]. It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify He by wherein the controller is further configured to electronically remove ripple in an output of the converter by controlling one or more switches of the three different phase modules as taught by Maeda in order of being able to reduce noise in the output. Regarding claim 4, He [e.g. Figs. 1 – 3] discloses wherein the controller is configured to control the one or more switches and the switching circuitry in response to measured parameters obtained from the NPC converter [e.g. paragraph 023 recites “The fault tolerant inverter 12 is connected to a microcontroller 26, which receives fault detection inputs 28 from the T-Type NPC inverter 14 and fault detection inputs 30 from the redundant phase leg 16. As will be described in further detail herein, the fault detection inputs may include measured voltages and/or currents within the fault tolerant inverter 12 which are used by the microcontroller 26 to operate the switches”]. Regarding claim 5, He [e.g. Figs. 1 – 3] discloses wherein the converter is an Active NPC (ANPC) DC to AC converter [e.g. claim 15 recites “wherein the inverter is at least one of a neutral-point-clamped (NPC) power converter, a T-type NPC power converter, or an active NPC power converter”]. Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Maeda and further in view of US Pub. No. 2013/0194840; (hereinafter Huselstein). Regarding claim 6, He fails to disclose wherein one or more of the three different phase modules includes a modified phase module having a combination of fast acting fuses and switches for rapid disconnect for a faulted one of the three phase modules connected to a neutral point of the NPC converter. Huselstein [e.g. Fig. 16] teaches wherein one or more of the three different phase modules [e.g. 2106] includes a modified phase module having a combination of fast acting fuses [e.g. 2114, 2116] and switches [e.g. 2128, 2131 ] for rapid disconnect for a faulted one of the three phase modules connected to a neutral point of the NPC converter [e.g. paragraph 275 recites “three circuits 2128, 2129, 2130 for aiding in the isolation of a main arm of the source, and three circuits 2131, 2132, 2133 for aiding in the isolation of a main arm of the neutral point.” Paragraph 0286 recites “The first and second internal cells 2162, 2164, connected in parallel, are nested in a third switching cell 2166 of which a different switch is connected to the first and second polarities 2139, 2140 by means of the fuses 2114, 2116 respectively”]. It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify He by wherein one or more of the three different phase modules includes a modified phase module having a combination of fast acting fuses and switches for rapid disconnect for a faulted one of the three phase modules connected to a neutral point of the NPC converter as taught by Huselstein in order of being able to aiding isolating of a main arm during a fault. Regarding claim 8, He discloses wherein the converter is configured to continue to operate after disconnect of the faulted one of the three phase modules [e.g. fault tolerant inverter, paragraph 033 recites “Once an open-circuit fault in IGBT Sa1 occurs, the Phase-A leg of the T-Type inverter will not be able to produce a positive voltage. This fault is exemplarily identified by the microcontroller 26, and the microcontroller 26 provides a control signal through the gate driver circuit 32 to close the positive redundant switch 54 and to close bi-directional midpoint switch 50 (Sa2, Sa3). In such operation, IGBT Sa1 (now with an open fault) is operationally replaced by positive redundant switch 54 (S1) from the redundant phase leg 16 and midpoint switch 50 (Sa2, Sa3). The other IGBTs on the redundant leg are held in an open (off) condition. As seen in FIG. 2, the current flow 62 provides the required positive voltage to the output terminal A through the positive redundant switch S1 and the midpoint switch 50 Sa2. As can be seen, during such fault-tolerant operation, the three-phase inverter can still output rated voltage, but will be operated as a two-level inverter”]. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Maeda, Huselstein and further in view of US Patent No. 7,787,217; (hereinafter Hu). Regarding claim 7, He fails to disclose wherein the switches are silicon controlled rectifiers. Hu [e.g. Figs. 5 - 6] teaches wherein the switches are silicon controlled rectifiers [e.g. col. 10, lines 28 – 37 recite “According to the embodiment of the present invention, a switching tube of the present invention may include, but is not limited to, a power device or a combination of different power devices, such as a metal oxide semiconductor (Metal Oxide Semiconductor, MOSFET), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), an integrated gate commutated thyristors (Integrated Gate Commutated Thyristors, IGCT) and a silicon controlled rectifier (Silicon Controlled Rectifier, SCR)”. Col. 11, lines 1 – 22 recite “The three three-level bridge arms 630 include a three-level bridge A, a three-level bridge arm B and a three-level bridge arm C. A circuit topology of each three-level bridge arm is shown in FIG. 5A and a sequence diagram of a driving signal is shown in FIG. 5B, which are not further described herein. An alternating current node of each three-level bridge arm is connected to a corresponding winding of the coupling inductor. A second switching tube Q2 and a third switching tube Q3 of each three-level bridge arm are connected in series between the Bus_N and the alternating current node of the three-level bridge arm. A first switching tube Q1 of each three-level bridge arm is connected between the Bus_+ of the direct current bus and the alternating current node of the three-level bridge arm. A fourth switching tube Q4 of each three-level bridge arm is connected between the Bus_− of the direct current bus and the alternating current node of the three-level bridge arm. The clamped neutral point of each three-level bridge arm is connected to the neutral point of the bleeder circuit. The neutral point of the bleeder circuit receives a reference voltage”]. It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify He by herein the switches are silicon controlled rectifiers as taught by Hu in order of being able to provide fast switching, high efficiency and reliability. Examiner's Note Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jan 06, 2025
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12749978
POWER STAGE CONTROLLER
2y 9m to grant Granted Sep 29, 2026
Patent 12744450
METHODS, SYSTEMS, AND DEVICES FOR SOFT SWITCHING OF POWER CONVERTERS
3y 3m to grant Granted Sep 22, 2026
Patent 12744460
VALLEY CURRENT MODE CONTROL FOR A VOLTAGE CONVERTER
3y 2m to grant Granted Sep 22, 2026
Patent 12744409
RESONANT REGULATING RECTIFIER
1y 11m to grant Granted Sep 22, 2026
Patent 12738850
METHOD FOR OPERATING A DC-DC CONVERTER FOR SUPPLYING AN ELECTROLYSIS DEVICE WITH ELECTRICAL OPERATING POWER
2y 4m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+11.3%)
2y 1m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month