DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 04/17/2026. Claims 1, 4, 17 and 20 have been amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 9, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Wang [US 2018/0357176 A1].
Claim 1 is rejected over Fromm and Wang.
Fromm teaches “A method, comprising: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory,” as “The present invention generally relates to offloading transactional memory accesses to a globally coherent memory system between compute nodes from processors in a compute node to a transactional memory agent that resides near the compute node.” [¶0003]
“the shared memory being shared by the plurality of nodes, the first address being an address within a shared memory section of a second node,” as “When the processor 103 in compute node 10 requires shared memory data located at the globally coherent memory controller 101 on compute node 20, ” [¶0052] (Node 10 and 20 indicates there are plurality of nodes)
“the first address being cached in a first cache of the first node, the executing, associated with a control signal, comprising:” as “Global coherent memory controller(s) 5 maintains logs identifying what data is stored in the cache hierarchy of processor 1 and what data is stored in the cache hierarchy of processor 6. Global coherent memory controller(s) 5 also maintains a record of the state of individual pieces of data contained within cache hierarchies .” [¶0050]
“fetching a value stored in the shared memory, at the first address” as “the processor 103 in compute node 10 instructs the transactional memory agent 102 on compute node 10 to fetch the data from compute node 20. ” [¶0052]
Fromm does not explicitly teach and replacing a cached value in the first cache of the first node with the value fetched from the shared memory based on the control signal.
However, Wang teaches “and replacing a cached value in the first cache of the first node with the value fetched from the shared memory based on the control signal.” as “Since named shared memory region 214 is essentially a passive entity that can be accessed by multiple SDC services simultaneously, in various embodiments each SDC service 212 can perform its caching activities with respect to region 214 in a manner that (1) avoids concurrency problems (i.e., avoids data corruption caused by interleaved reads/writes) and (2) implements a consistent cache replacement algorithm/policy across application instances.” [¶0018]
Fromm and Wang are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm and Wang before him/her, to modify the teachings of Fromm to include the teachings of Wang with the motivation of the advantages of both kernel bypass (i.e., elimination of context switching overhead) and a shared data cache (i.e., improved I/O performance via data sharing and more efficient cache space usage) can be realized at the same time. [Wang, ¶0012]
Claim 9 is rejected over Fromm and Wang.
Fromm teaches “wherein the executing comprises executing, by a processor of the first node, a global store instruction, the global store instruction being part of an instruction set architecture of the processor of the first node.” as “ Main memory 1020 stores, in part, instructions and data for execution by processor 1010. Main memory 1020 can store the executable code when in operation.” [¶0077]
Claim 17 recites a system and rejected over Fromm and Wang under the same rationale of anticipation of claim 1.
Claim 20 recites a system and rejected over Fromm and Wang under the same rationale of anticipation of claim 1.
Claim(s) 2-3 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Wang [US 2018/0357176 A1] and in further view of Cantin et al. [US 2010/0281221 A1].
Claim 2 is rejected over Fromm, Wang and Cantin.
The combination of Fromm and Wang does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing further comprises invalidating the first address in a second cache of the first node.” as “When there is a hit for the cache line, in some embodiments the cache line is transferred to the second node and invalidated in the first node,” [¶0032]
Fromm, Wang and Cantin are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm, Wang and Cantin before him/her, to modify the teachings of combination of Fromm and Wang to include the teachings of Cantin with the motivation of there is a need in the art for reducing the impact of cache misses, reducing the impact of microprocessor competition, and improving microprocessor communications in a shared memory computing system. [Cantin, ¶0014]
Claim 3 is rejected over Fromm, Wang and Cantin.
The combination of Fromm and Wang does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing comprises executing, by a processor of the first node, a global load instruction, the global load instruction being part of an instruction set architecture of the processor of the first node.” as “while the administrative tools may control the scheduling and loading of programs, tasks, data, and jobs onto the processing nodes 42, including loading programs, tasks, data, and jobs onto computing core of each core 12 of each processing node 42. ” [¶0044]
Claim 18 is rejected over Fromm, Wang and Cantin under the same rationale of rejection of claim 2.
Claim 19 is rejected over Fromm, Wang and Cantin under the same rationale of rejection of claim 3.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Wang [US 2018/0357176 A1] in further view of Cantin et al. [US 2010/0281221 A1] and yet in further view of SALISBURY et al. [US 2016/0062890 A1].
Claim 4 is rejected over Fromm, Wang, Cantin and SALISBURY.
The combination of Fromm, Wang and Cantin does not explicitly teach wherein the executing comprises, asserting, by the processor, the control signal indicating that the global load instruction is being executed as a global instruction.
However, SALISBURY teaches “wherein the executing comprises, asserting, by the processor, the control signal indicating that the global load instruction is being executed as a global instruction.” as “If the eviction buffer 52 is full and another transaction misses in the snoop filter so it is not possible to allocate a new entry, then the snoop filter may assert a retry signal 70 which signals to the coherency control circuitry 22 that the transaction which missed in the snoop filter 24 should be retried later.” [¶0104]
Fromm, Wang, Cantin and SALISBURY are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm, Wang, Cantin and SALISBURY before him/her, to modify the teachings of combination of Fromm, Wang and Cantin to include the teachings of SALISBURY with the motivation of reducing the circuit area and increasing performance in the snoop filter more than compensates for the additional overhead in taking any measures for deadlock avoidance. [SALISBURY, ¶0067]
Claim 5 is rejected over Fromm, Wang, Cantin and SALISBURY.
The combination of Fromm and Wang does not explicitly teach wherein the first node is configured to route the control signal to a cache controller of the first node.
However, Cantin teaches “wherein the first node is configured to route the control signal to a cache controller of the first node.” as “The functionality of the management nodes 54 and/or service nodes 58 may be combined in a control subsystem operable to receive, manage, schedule, redistribute, and otherwise control jobs for the processing nodes 42.” [¶0044]
Claim 6 is rejected over Fromm, Wang, Cantin and SALISBURY.
The combination of Fromm and Wang does not explicitly teach wherein the cache controller is configured to perform a backing store fetch in response to the control signal.
However, Cantin teaches “wherein the cache controller is configured to perform a backing store fetch in response to the control signal.” as “Presence data in the PRB 88 may remain in the PRB 88 until that memory region or a cache line thereof is fetched to the caches 83, 84, fetched by another node 42, or evicted to make room for additional presence data (e.g., presence data in the PRB 88 is evicted to make room for additional presence data by way of a least-recently-used,” [¶0053]
Claim 7 is rejected over Fromm, Wang, Cantin and SALISBURY.
The combination of Fromm and Wang does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing further comprises invalidating the first address in a second cache of the first node.” as “When there is a hit for presence data associated with the memory request in the prefetch region buffer and/or when there is a hit for presence data associated with a memory region(s) adjacent to the memory region associated with the memory request in the prefetch region buffer ("Yes" branch of decision block 168), presence data associated with the memory request from the prefetch region buffer and/or presence data associated with the memory region(s) adjacent to the memory region associated with the memory request may be invalidated from the prefetch region buffer (block 192).” [¶0071]
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Wang [US 2018/0357176 A1] and in further view of Hong et al. [US 2014/0258635 A1].
Claim 8 is rejected over Fromm, Wang and Hong.
The combination of Fromm and Wang does not explicitly teach further comprising: executing, by the first node, a global store to a second address of the shared memory, the second address being cached in the first cache, the executing comprising: storing a value in the shared memory, at the second address.
However, Hong teaches “further comprising: executing, by the first node, a global store to a second address of the shared memory, the second address being cached in the first cache, the executing comprising: storing a value in the shared memory, at the second address.” as “each cache entry may store a memory address where the corresponding data item is located in shared memory 130.” [¶0026]
Fromm, Wang and Hong are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm, Wang and Hong before him/her, to modify the teachings of combination of Fromm and Wang to include the teachings of Hong with the motivation of invalidation may be performed in just a few cycles, whereas a prior invalidation approach involved multiple invalidate instructions, where each invalidate instruction targets a different cache entry and requires one or more cycles. [Hong, ¶0060]
Allowable Subject Matter
Claims 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 recites “executing, by the first node, a global atomic instruction on a third address of the shared memory, the executing comprising: executing the global atomic instruction by a controller of a last level cache of the first node, the controller of the last level cache of the first node being a globally unique point of serialization of instructions.”
Closest prior arts of record do not appear to teach or fairly suggest executing a global atomic instruction wherein the controller of the cache is a unique point of serialization instructions. Therefore, claim 10 is considered to contain allowable subject matter. Claims 11-16 are objected as being dependent on claim 10.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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