DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fromm [US 2014/0068201 A1].
Regrading claim 1, Fromm teaches “A method, comprising: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory,” as “The present invention generally relates to offloading transactional memory accesses to a globally coherent memory system between compute nodes from processors in a compute node to a transactional memory agent that resides near the compute node.” [¶0003]
“the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node,” as “When the processor 103 in compute node 10 requires shared memory data located at the globally coherent memory controller 101 on compute node 20, ” [¶0052]
“the first address being cached in a first cache of the first node, the executing comprising:” as “Global coherent memory controller(s) 5 maintains logs identifying what data is stored in the cache hierarchy of processor 1 and what data is stored in the cache hierarchy of processor 6. Global coherent memory controller(s) 5 also maintains a record of the state of individual pieces of data contained within cache hierarchies .” [¶0050]
“fetching a value stored in the shared memory, at the first address.” as “the processor 103 in compute node 10 instructs the transactional memory agent 102 on compute node 10 to fetch the data from compute node 20. ” [¶0052]
Regrading claim 9, Fromm teaches “wherein the executing comprises executing, by a processor of the first node, a global store instruction, the global store instruction being part of an instruction set architecture of the processor of the first node.” as “ Main memory 1020 stores, in part, instructions and data for execution by processor 1010. Main memory 1020 can store the executable code when in operation.” [¶0077]
Claim 17 recites a system and anticipated by Fromm under the same rationale of anticipation of claim 1.
Claim 20 recites a system and anticipated by Fromm under the same rationale of anticipation of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Cantin et al. [US 2010/0281221 A1].
Claim 2 is rejected over Fromm and Cantin.
Fromm does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing further comprises invalidating the first address in a second cache of the first node.” as “When there is a hit for the cache line, in some embodiments the cache line is transferred to the second node and invalidated in the first node,” [¶0032]
Fromm and Cantin are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm and Cantin before him/her, to modify the teachings of Fromm to include the teachings of Cantin with the motivation of there is a need in the art for reducing the impact of cache misses, reducing the impact of microprocessor competition, and improving microprocessor communications in a shared memory computing system. [Cantin, ¶0014]
Claim 3 is rejected over Fromm and Cantin.
Fromm does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing comprises executing, by a processor of the first node, a global load instruction, the global load instruction being part of an instruction set architecture of the processor of the first node.” as “while the administrative tools may control the scheduling and loading of programs, tasks, data, and jobs onto the processing nodes 42, including loading programs, tasks, data, and jobs onto computing core of each core 12 of each processing node 42. ” [¶0044]
Claim 18 is rejected over Fromm and Cantin under the same rationale of rejection of claim 2.
Claim 19 is rejected over Fromm and Cantin under the same rationale of rejection of claim 3.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Cantin et al. [US 2010/0281221 A1] and in further view of SALISBURY et al. [US 2016/0062890 A1].
Claim 4 is rejected over Fromm, Cantin and SALISBURY.
The combination of Fromm and Cantin does not explicitly teach wherein the execution comprises, asserting, by the processor, a control signal indicating that a global instruction is being executed.
However, SALISBURY teaches “wherein the execution comprises, asserting, by the processor, a control signal indicating that a global instruction is being executed.” as “If the eviction buffer 52 is full and another transaction misses in the snoop filter so it is not possible to allocate a new entry, then the snoop filter may assert a retry signal 70 which signals to the coherency control circuitry 22 that the transaction which missed in the snoop filter 24 should be retried later.” [¶0104]
Fromm, Cantin and SALISBURY are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm, Cantin and SALISBURY before him/her, to modify the teachings of combination of Fromm and Cantin to include the teachings of SALISBURY with the motivation of reducing the circuit area and increasing performance in the snoop filter more than compensates for the additional overhead in taking any measures for deadlock avoidance. [SALISBURY, ¶0067]
Claim 5 is rejected over Fromm, Cantin and SALISBURY.
Fromm does not explicitly teach wherein the first node is configured to route the control signal to a cache controller of the first node.
However, Cantin teaches “wherein the first node is configured to route the control signal to a cache controller of the first node.” as “The functionality of the management nodes 54 and/or service nodes 58 may be combined in a control subsystem operable to receive, manage, schedule, redistribute, and otherwise control jobs for the processing nodes 42.” [¶0044]
Claim 6 is rejected over Fromm, Cantin and SALISBURY.
Fromm does not explicitly teach wherein the cache controller is configured to perform a backing store fetch in response to the control signal.
However, Cantin teaches “wherein the cache controller is configured to perform a backing store fetch in response to the control signal.” as “Presence data in the PRB 88 may remain in the PRB 88 until that memory region or a cache line thereof is fetched to the caches 83, 84, fetched by another node 42, or evicted to make room for additional presence data (e.g., presence data in the PRB 88 is evicted to make room for additional presence data by way of a least-recently-used,” [¶0053]
Claim 7 is rejected over Fromm, Cantin and SALISBURY.
Fromm does not explicitly teach wherein the executing further comprises invalidating the first address in a second cache of the first node.
However, Cantin teaches “wherein the executing further comprises invalidating the first address in a second cache of the first node.” as “When there is a hit for presence data associated with the memory request in the prefetch region buffer and/or when there is a hit for presence data associated with a memory region(s) adjacent to the memory region associated with the memory request in the prefetch region buffer ("Yes" branch of decision block 168), presence data associated with the memory request from the prefetch region buffer and/or presence data associated with the memory region(s) adjacent to the memory region associated with the memory request may be invalidated from the prefetch region buffer (block 192).” [¶0071]
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fromm [US 2014/0068201 A1] in view of Hong et al. [US 2014/0258635 A1].
Claim 8 is rejected over Fromm and Hong.
Fromm does not explicitly teach further comprising: executing, by the first node, a global store to a second address of the shared memory, the second address being cached in the first cache, the executing comprising: storing a value in the shared memory, at the second address.
However, Hong teaches “further comprising: executing, by the first node, a global store to a second address of the shared memory, the second address being cached in the first cache, the executing comprising: storing a value in the shared memory, at the second address.” as “each cache entry may store a memory address where the corresponding data item is located in shared memory 130.” [¶0026]
Fromm and Hong are analogous arts because they teach shared data management in multi node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Fromm and Hong before him/her, to modify the teachings of Fromm to include the teachings of Hong with the motivation of invalidation may be performed in just a few cycles, whereas a prior invalidation approach involved multiple invalidate instructions, where each invalidate instruction targets a different cache entry and requires one or more cycles. [Hong, ¶0060]
Allowable Subject Matter
Claims 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 recites “executing, by the first node, a global atomic instruction on a third address of the shared memory, the executing comprising: executing the global atomic instruction by a controller of a last level cache of the first node, the controller of the last level cache of the first node being a globally unique point of serialization of instructions.”
Closest prior arts of record do not appear to teach or fairly suggest executing a global atomic instruction wherein the controller of the cache is a unique point of serialization instructions. Therefore, claim 10 is considered to contain allowable subject matter. Claims 11-16 are objected as being dependent on claim 10.
Conclusion
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132