DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cantin et al. [US 2010/0281221 A1] in view of Chachad et al. [US 2020/0371935 A1].
Claim 1 is rejected over Cantin and Chachad.
Cantin teaches “A method, comprising: executing, by a first node of a plurality of nodes, a global clean,” as “A method, circuit arrangement, and design structure for prefetching data for responding to a memory request, in a shared memory computing system of the type that includes a plurality of nodes, is provided.” [Abstract]
“the executing comprising: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and” as “The second letter indicates whether other nodes 42 of the system 40 have shared cache lines associated with the memory region ("invalid, or "I," if the memory region is not shared, or "clean" if there are unmodified copies of caches lines associated with the memory region) or modified ("dirty," or "D") copies of the cache lines associated with the memory region.” [¶0061]
Cantin does not explicitly teach in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.
However, Chachad teaches “in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.” as “if the global operation is the writeback operation, after modified cache lines in the L2 cache 324 are written back to their endpoint, the L2 controller 320 queries the coherence state for the lines in the L2 cache 324 and updates the coherence state for modified cache lines to be shared.” [¶0095]
Cantin and Chachad are analogous arts because they teach cache hierarchy and coherence management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Cantin and Chachad before him/her, to modify the teachings of Cantin to include the teachings of Chachad with the motivation of global cache operations are pipelined to take advantage of the banked configuration of the L2 cache subsystem. [Chachad, ¶0092]
Claim 2 is rejected over Cantin and Chachad.
Cantin does not explicitly teach wherein the executing further comprises changing a state of the first cached value from modified to exclusive.
However, Chachad teaches “wherein the executing further comprises changing a state of the first cached value from modified to exclusive.” as “A cache line having a cache coherence state of modified indicates that the cache line is modified with respect to main memory (e.g., DDR 110), and the cache line is held exclusively in the current cache (e.g., the L2 cache 324). A modified cache coherence state also indicates that the cache line is explicitly not present in any other caches (e.g., L1 or L3 caches).” [¶0050]
Claim 3 is rejected over Cantin and Chachad.
Cantin does not explicitly teach the executing further comprises determining that the first cached value is a modified cached copy of data in a portion of the shared memory that is remote from the first node, and
the writing back is further in response to determining that the first cached value is a modified cached copy of data in a portion of the shared memory that is remote from the first node.
However, Chachad teaches “the executing further comprises determining that the first cached value is a modified cached copy of data in a portion of the shared memory that is remote from the first node, and” as “A cache line having a cache coherence state of shared indicates that the cache line is not modified with respect to main memory (e.g., DDR 110). A shared cache state also indicates that the cache line may be present in multiple caches (e.g., caches in addition to the L2 cache 324).” [¶0052]
“the writing back is further in response to determining that the first cached value is a modified cached copy of data in a portion of the shared memory that is remote from the first node.” as “ Victims transfer modified data to the next level of the hierarchy. In some cases, victims are further propagated to numerically-higher levels of the cache hierarchy (e.g., if the L2 controller 310 sends a victim to the L2 controller 320 for an address in the DDR 110, and the line is not present in the L2 cache 324, the L2 controller 320 forwards the victim to the L3 controller 309). ” [¶0056]
Claim 4 is rejected over Cantin and Chachad.
Cantin teaches “wherein the determining comprises determining that a global bit associated with the first cached value is set.” as “ the presence data includes a memory region bit-mask indicating each cache line from the memory region cached in the first node.” [¶0035]
Claim 5 is rejected over Cantin and Chachad.
Cantin teaches “further comprising executing, by the first node, a global invalidate,” as “the at least one cached cache line may be sent to the second node 42 and invalidated in the first node 42” [¶0052]
“the executing comprising: determining that a second cached value in the cache of the first node is a cached copy of data in the shared memory; and” as “ the state of a memory region of a first node may be that it is invalid (e.g., that there is no such memory region) or that it is shared.” [¶0052]
“in response to determining that the second cached value is a cached copy of data in the shared memory, invalidating the second cached value.” as “ the memory region may be either clean (e.g., the first node 42 has not modified a cache line of the memory region) or dirty (e.g., the first node 42 has modified a cache line of the memory region). In that example, when the first node 42 receives a memory request from a second node 42 for at least one cached cache line from a memory region in the first node 42, a copy of the presence data for that memory region may be sent to the second node 42, the at least one cached cache line may be sent to the second node 42 and invalidated in the first node 42, and/or the state of that memory region may be changed in the first node 42 to a shared state. ” [¶0052]
Claim 6 is rejected over Cantin and Chachad.
Cantin teaches “wherein the determining comprises determining that a global bit associated with the first cached value is set.” as “ the presence data includes a memory region bit-mask indicating each cache line from the memory region cached in the first node.” [¶0035]
Claim 7 is rejected over Cantin and Chachad.
Cantin does not explicitly teach further comprising executing, by the first node, a global flush,
the executing comprising: determining that a third cached value in the cache of the first node is a cached copy of data in the shared memory; and
in response to determining that the third cached value is a cached copy of data in the shared memory: copying the third cached value to the shared memory, and invalidating the third cached value.
However, Chachad teaches “further comprising executing, by the first node, a global flush,” as “The method continues in block 714 to determine whether all transactions have been flushed from the pipeline. In response to the L2 controller 320 determining that the pipeline does not contain any more pending transactions, the method 700 continues to block 716.” [¶0100]
“the executing comprising: determining that a third cached value in the cache of the first node is a cached copy of data in the shared memory; and” as “ if an application does not need to use the L3 SRAM as shared L2 or L3 memory (e.g., to enable the L2 cache subsystem 306 to cache addresses in the L3 SRAM address region), the physical L3 SRAM region is mapped (e.g., through the MMU described above) to an external, virtual address.” [¶0135]
“in response to determining that the third cached value is a cached copy of data in the shared memory: copying the third cached value to the shared memory, and invalidating the third cached value.” as “ the L2 controller 320 invalidates each line in the L2 cache 324 that corresponds to the L3 SRAM address region. In another example, the L2 controller 320 writes back each line in the L2 cache 324 that corresponds to the L3 SRAM address region.” [¶0142]
Claim 9 is rejected over Cantin and Chachad.
Cantin teaches “wherein the executing further comprises determining that the third cached value is a modified cached copy of data in the shared memory.” as “ The second letter indicates whether other nodes 42 of the system 40 have shared cache lines associated with the memory region ("invalid, or "I," if the memory region is not shared, or "clean" if there are unmodified copies of caches lines associated with the memory region) or modified ("dirty," or "D") copies of the cache lines associated with the memory region.” [¶0061]
Claim 10 is rejected over Cantin and Chachad.
Cantin does not explicitly teach further comprising executing, by the first node, a global flush,
the executing comprising: determining that a third cached value in the cache of the first node is an unmodified cached copy of data in the shared memory; and
in response to determining that the third cached value is an unmodified cached copy of data in the shared memory, invalidating the third cached value.
However, Chachad teaches “further comprising executing, by the first node, a global flush,” as “The method continues in block 714 to determine whether all transactions have been flushed from the pipeline. In response to the L2 controller 320 determining that the pipeline does not contain any more pending transactions, the method 700 continues to block 716.” [¶0100]
“the executing comprising: determining that a third cached value in the cache of the first node is an unmodified cached copy of data in the shared memory; and” as “ when a new allocation takes place in the L1 main cache 314, the current line in the set is moved to the L1 victim cache 316, regardless of whether the line is clean (e.g., unmodified) or dirty (e.g., modified).” [¶0057]
“in response to determining that the third cached value is an unmodified cached copy of data in the shared memory, invalidating the third cached value.” as “ the L2 controller 320 invalidates each line in the L2 cache 324 that corresponds to the L3 SRAM address region. In another example, the L2 controller 320 writes back each line in the L2 cache 324 that corresponds to the L3 SRAM address region.” [¶0142]
Claim 11 is rejected over Cantin and Chachad under the same rationale of rejection of claim 1.
Claim 12 is rejected over Cantin and Chachad under the same rationale of rejection of claim 2.
Claim 13 is rejected over Cantin and Chachad under the same rationale of rejection of claim 3.
Claim 14 is rejected over Cantin and Chachad under the same rationale of rejection of claim 4.
Claim 15 is rejected over Cantin and Chachad under the same rationale of rejection of claim 5.
Claim 16 is rejected over Cantin and Chachad under the same rationale of rejection of claim 6.
Claim 17 is rejected over Cantin and Chachad under the same rationale of rejection of claim 7.
Claim 19 is rejected over Cantin and Chachad under the same rationale of rejection of claim 9.
Claim 20 is rejected over Cantin and Chachad under the same rationale of rejection of claim 1.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cantin et al. [US 2010/0281221 A1] in view of Chachad et al. [US 2020/0371935 A1] and in further view of Ivester et al. [US 11,074,113 B1].
Claim 8 is rejected over Cantin, Chachad and Ivester.
The combination of Cantin and Chachad does not explicitly teach wherein the determining comprises determining that a global bit associated with the first cached value is set.
However, Ivester teaches “wherein the determining comprises determining that a global bit associated with the first cached value is set.” as “the compute node 116 sets the global flag bit 330 for the selected local cache slot to local (block 525) to prevent compute nodes 116 in other storage engines 118 from competing for access to the selected local cache slot. ” [Col 8, lines 14-18]
Cantin, Chachad and Ivester are analogous arts because they teach cache hierarchy and coherence management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Cantin, Chachad and Ivester before him/her, to modify the teachings of combination of Cantin and Chachad to include the teachings of Ivester with the motivation of regulate access to cache slots, other forms of locks or mutexes may be used to enforce a mutual exclusion concurrency control policy on the cache slots. [Ivester, Col 7, lines 4-6]
Claim 18 is rejected over Cantin, Chachad and Ivester under the same rationale of rejection of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MASUD K KHAN/ Primary Examiner, Art Unit 2132
Prosecution Insights