DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 08/05/2026. Claims 1, 10 and 19 have been amended.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 19 recites “each of the nodes comprising means for processing”. Examiner reviewed and drawings and spec and concluded element 115 in every node of Fig. 1 is the means for processing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 10-11 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. [US 2012/0124297 A1] in view of Jung et al. [US 11,537,516 B1].
Claim 1 is rejected over Chung and Jung.
Chung teaches “A method, comprising: writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory” as “If system management software 205 reschedules an application executing on processing node 102 for execution at a later time, system management software 205 reassigns memory requests for the application again to processing node 102” [¶0019] (Scheduling of execution is a sequence of time steps)
“the shared memory being shared by the nodes,” as “In at least one embodiment of processing node 102, cache coherence may be performed using any suitable cache coherence mechanism that maintains consistency between all caches in a system of distributed shared memory according to a particular consistency model” [¶0030] (Shared memory are shared among nodes)
“wherein: each of the nodes comprises a hardware-maintained coherence domain and is connected to the other nodes, and” as “processing node 102 establishes a local coherence domain corresponding to each core” [¶0029] (Hardware driven coherence is recited)
“each of the nodes comprises a respective portion of the shared memory.” as [Fig. 2, element 216] (Fig. 2 shows a single node among all nodes. Element 216 is the shared global memory inside that node.)
Chung does not explicitly teach such that, during each of the time steps, only one node of the plurality of nodes modifies data in a location of the shared memory,
However, Jung teaches “such that, during each of the time steps, only one node of the plurality of nodes modifies data in a location of the shared memory,” as “write requests may be received by various nodes, each of which may write (or initiate writing of) the change to the transaction log. Small inconsistencies in the system clocks of the nodes writing the changes to the transaction log can result in some changes being written with a transaction sequencer that is less than or otherwise sequentially prior to the transaction sequencer of a change previously written to the transaction log by a different node.” [Col 7, lines 30-40]
Chung and Jung are analogous arts because they teach storage system and cache memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chung and Jung before him/her, to modify the teachings of Chung to include the teachings of Jung with the motivation of ensuring monotonic writes using the routine 600 helps to ensure data consistency among caches of the persistent data, such that stale data is less likely to be accessed. [Jung, Col 20, lines 33-36]
Claim 2 is rejected over Chung and Jung.
Chung teaches “modifying, by a first node of the plurality of nodes, a value at a first address of the shared memory, and storing a record of the modifying.” as “ as soon as one processor modifies the value of the memory location, the other processor will be operating on an out-of-date copy of the contents of the memory location. A mechanism for notifying all processors of the multi-processor system of changes to shared memory locations is referred to as a "memory coherence mechanism."” [¶0004]
Claim 10 is rejected over Chung and Jung under the same rationale of rejection of claim 1.
Claim 11 is rejected over Chung and Jung under the same rationale of rejection of claim 2.
Claim 19 is rejected over Chung and Jung under the same rationale of rejection of claim 1.
Claim 20 is rejected over Chung and Jung under the same rationale of rejection of claim 2.
Claim(s) 3-5 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. [US 2012/0124297 A1] in view of Jung et al. [US 11,537,516 B1] and in further view of Na et al. [US 2021/0232501 A1].
Claim 3 is rejected over Chung, Jung and Na.
The combination of Chung and Jung does not explicitly teach wherein the storing of the record comprises storing the record in a hash table.
However, Na teaches “wherein the storing of the record comprises storing the record in a hash table.” as “Each set of hash tables, from the k sets of hash tables, includes a hash table for each of p caches.” [¶0018]
Chung, Jung and Na are analogous arts because they teach storage system and cache memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chung, Jung and Na before him/her, to modify the teachings of combination of Chung and Jung to include the teachings of Na with the motivation of there is a need for a better approach for controlling the size of coherence directories as computing architectures increase the number and size of caches. [Na, ¶0005]
Claim 4 is rejected over Chung, Jung and Na.
The combination of Chung and Jung does not explicitly teach wherein the storing of the record in the hash table comprises: hashing the first address to generate a hashed address, and
storing a node identifier of the first node at the hashed address, in the hash table.
However, Na teaches “wherein the storing of the record in the hash table comprises: hashing the first address to generate a hashed address, and” as “one or more of the bits in the hash tables may have been set by the hashing of one or more other memory addresses.” [¶0025]
“storing a node identifier of the first node at the hashed address, in the hash table.” as “An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory.” [¶0014]
Claim 5 is rejected over Chung, Jung and Na.
Chung teaches “modifying, by a second node of the plurality of nodes, the value at the first address of the shared memory.” as “In yet another cache coherence mechanism, i.e., snarfing, a cache controller of a first processor of a multi-processor system monitors both address and data lines in an attempt to update a copy of data in a cache of a processor when another processor modifies a corresponding location in memory.” [¶0005]
Claim 12 is rejected over Chung, Jung and Na under the same rationale of rejection of claim 3.
Claim 13 is rejected over Chung, Jung and Na under the same rationale of rejection of claim 4.
Claim 14 is rejected over Chung, Jung and Na under the same rationale of rejection of claim 5.
Claim(s) 6-9 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. [US 2012/0124297 A1] in view of Jung et al. [US 11,537,516 B1], in further view of Na et al. [US 2021/0232501 A1] and yet in further view of Jayaprakash et al. [US 2009/0309734 A1].
Claim 6 is rejected over Chung, Jung, Na and Jayaprakash.
The combination of Chung, Jung and Na does not explicitly teach determining that a violation has occurred.
However, Jayaprakash teaches “determining that a violation has occurred.” as “At 460, a query is presented to determine if the particular tag is allowed in this zone. In one example, zone violation information is accessed from TAGS HASH TABLE. ” [¶0052]
Chung, Jung, Na and Jayaprakash are analogous arts because they teach storage system and cache memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chung, Jung, Na and Jayaprakash before him/her, to modify the teachings of combination of Chung, Jung and Na to include the teachings of Jayaprakash with the motivation of existing tag systems are prone to errors. [Jayaprakash, ¶0003]
Claim 7 is rejected over Chung, Jung, Na and Jayaprakash.
The combination of Chung, Jung and Na does not explicitly teach wherein the determining that a violation has occurred further comprises: hashing the first address to generate the hashed address; and
reading a node identifier from the hashed address in the hash table.
However, Jayaprakash teaches “wherein the determining that a violation has occurred further comprises: hashing the first address to generate the hashed address; and” as “At 460, a query is presented to determine if the particular tag is allowed in this zone. In one example, zone violation information is accessed from TAGS HASH TABLE. ” [¶0052]
“reading a node identifier from the hashed address in the hash table.” as “Processor 120 reads a job from job queue 110 and performs additional processing, including for example, evaluating a hash table, and storing results in database 75 or memory 130.” [¶0026]
Claim 8 is rejected over Chung, Jung, Na and Jayaprakash.
The combination of Chung, Jung and Na does not explicitly teach wherein the determining that a violation has occurred further comprises determining that the node identifier read from the hash table at the hashed address is different from a node identifier of the second node.
However, Jayaprakash teaches “wherein the determining that a violation has occurred further comprises determining that the node identifier read from the hash table at the hashed address is different from a node identifier of the second node.” as “Some examples of conditions or events include detection of presence at a location (AT), detection of entry or exit, or detection of a condition warranting an alarm (such as a zone violation).” [¶0019]
Claim 9 is rejected over Chung, Jung, Na and Jayaprakash.
The combination of Chung, Jung and Na does not explicitly teach further comprising raising an exception.
However, Jayaprakash teaches “further comprising raising an exception.” as “The violation signal can be sent to at least one of computer database 75, memory 130, and computer 70 (FIG. 1).” [¶0049]
Claim 15 is rejected over Chung, Jung, Na and Jayaprakash under the same rationale of rejection of claim 6.
Claim 16 is rejected over Chung, Jung, Na and Jayaprakash under the same rationale of rejection of claim 7.
Claim 17 is rejected over Chung, Jung, Na and Jayaprakash under the same rationale of rejection of claim 8.
Claim 18 is rejected over Chung, Jung, Na and Jayaprakash under the same rationale of rejection of claim 9.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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