DETAILED ACTION
Terminal Disclaimer
The terminal disclaimer, approved 7/10/2026, has overcome the previously presented double patenting rejections.
Claim Objections
Claims 7 and 16 are objected to because of the following informalities: Both claims include the limitation, “…includes transferring the data a persistent memory associated with the storage device…” at line 3. Both claims should be amended to read, “includes transferring the data from a persistent memory associated with the storage device…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 12 and 17 each include a limitation describing, “transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data”. Paragraph [0087] of the originally file specification states, “the disclosed system can transfer data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host”. The two ideas are fundamentally different. The claimed limitation appears to suggest that an application executing on the host executes a data operation on data that causes the data to transfer. However, the specification appears to describe that the application executing on the host performs a data operation on the second memory that causes the data to transfer. While the specification appears to describe pulling the data from the first memory, by executing a data operation on the second memory, the claim describes pushing the data out of the first memory by executing a data operation on said data. The dependent claims inherit and does not correct this issue. The Examiner suggests amending the claims to align with the invention described in the originally filed specification or to particularly point out specific citations that are believed to support the claimed limitation.
Response to Arguments
Applicant agues, with respect to claims 1 – 20, that the Examiner erred in rejecting the claims under 35 U.S.C 112(a). While the claims were amended the argument is still relevant to the underlying problem identified by the current rejection. Specifically, Applicant alleges that transferring data between the first and second memories (whether copying, migrating, or storing) is a data operation on the data (in the second memory), and therefore provides written description support for the language of the claims. Examiner believes that this interpretation does not make sense when considering the next limitation in the claim. The next limitation states, “wherein the storage device includes a processing element to execute an offload function to accelerate the data operation.” Applicant’s argument appears to suggest that the “data operation” as claimed may just be copying, migrating, or storing, that would cause the data to transfer. However mere data movement is not what the specification describes as a data operation to be accelerated. Paragraph [0082] of the originally filed specification discloses decryption by a first offloaded program, analysis and filtering by another offload program. The “data operation” as claimed must also be the data operation that is accelerated by an offload function as well as can be accelerated by an offload function.
Prior Art Comment
The prior art of record does not teach or suggest the claims as written.
The closest prior art reference suggesting the data transfer as presented in paragraph [0087] of the originally filed specification is Costa et al. US Patent Application Publication No. 2020/0117517 (previously cited in PTO-892 mailed 4/8/2026, herein after referred to as Costa). Costa describes that a host user process is a process executed by the host processor, which resides at the user space level of the operating system and is initiated by a user (e.g., any custom application running on the operating system). The host user processor may write data to the host memory and/or to the computational storage device (page 3, paragraph [0043]). The computational storage device includes an embedded computer. The embedded computer may be designed for data operations or analytics, such as search and analysis of a large volume of unstructured data (page 3, paragraph [0046]). The embedded computer performs querying of data. For example, a query may consist of a request (e.g., from a host user process) to find a text word, and/or the number of occurrences of that text word in the computational storage device (page 4, paragraph [0047]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Ramachandran et al. US Patent Application Publication No. 2022/0206869 (previously cited in PTO-892 mailed 4/8/2026) describes the memory controller 106 is also used by the host 102 for offloading tasks for remote execution. In these examples, an offload task is a set of instructions or commands that direct a device external to the computing device 150 to carry out a sequence of operations. In this way, the workload on the cores 104 is alleviated by offloading the task for execution on the external device. For example, the offload task may be a processing-in-memory (PIM) task that includes a set of instructions or commands that direct a PIM device to carry out a sequence of operations on data stored in a PIM-enabled memory device (page 2, paragraph [0021]). However, Ramachandran does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation. Krasner et al. US Patent Application Publication No. 2020/0042234 (previously cited in PTO-892 mailed 4/8/2026) describes any one of the host computers 14a-14n may issue a data request to the data storage system 12 to perform a data operation. For example, an application executing on one of the host computers 14a-14n may perform a read or write operation resulting in one or more data requests to the data storage system 12 (page 4, paragraph [0028]). Furthermore, FIG. 5 is a block diagram illustrating an example of a method 500 of offloading processing according to embodiments of the invention. Other embodiments of a method of offloading processing, for example, variations of method 500, are possible and are intended to fall within the scope of the invention. Method 500 may be implemented on a device (e.g., the storage system 300) having a plurality of primary processors (e.g., corresponding to BEs 304) connected to one or more storage slots (e.g., NVMe-enabled storage slots 310) across a switch fabric (e.g., a PCIe fabric 316) (page 7, paragraph [0053]). However, Krasner does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation. Gao et al. US Patent Application Publication No. 2020/0310694 describes that the processor 216 of the heterogeneous computing system 212 may also be used to analyze data stored on host storage 208. The data moves from the host storage 208 to the host memory 206 along path 228 and then from the host memory 206 to the memory 218 of the heterogeneous computing system 212 along path 232 (generally through the peripheral interface 240, the switch 210, and the peripheral interface 242). Finally, the data moves from the memory 218 of the heterogeneous computing system 212 to the processor 216 for processing. For some data-intensive tasks, this cycle of data movement may occur more than once to execute a single command. For example, the data used as input for a computational task may use more storage space than is available on the memory 218 of the heterogeneous computing system 212. Movement of data between the host 106 and the heterogeneous computing system 212, especially repeated movement, may slow total computation time for tasks with large amounts of input data. (page 4, paragraph [0057]). However, Gao does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation. Costa et al. US Patent Application Publication No. 2020/0117517 (previously cited in PTO-892 mailed 4/8/2026) describes the embedded computer 300 may be designed for data operations or analytics, such as search and analysis of a large volume of unstructured data. The embedded 300 may include, for example, a reconfigurable digital signal processing (DSP) core containing arithmetic and logic units and other dedicated hardware units that may be used to perform data analytics, and other operations such as compression, decompression, encryption, and decryption (page 4, paragraph [0046]). However, Costa does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation. Mesnier et al. US Patent Application Publication No. 2022/0188028 (previously cited in PTO-892 mailed 4/8/2026) describes that in some embodiments, the compute offload command sent at the block 206 may include one or more NVMe commands. In some embodiments, the compute offload command may be a fused NVMe command that includes two opcodes. In some embodiments, the fused NVMe command may include a first opcode that may be used to transfer the compute descriptor from a host to a block based storage device, followed by a second opcode that may be used to transfer a result back to the host from the block based storage device (page 5, paragraph [0085]). However, Mesnier does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation. Jones US Patent Application Publication No. 2022/0236911 (previously cited in PTO-892 mailed 4/8/2026) describes the routine 400 includes step 402, where a data definition is received associated with a computational storage operation to be performed in the CSD 120. For example, the host 108 may request execution of a computational storage program from the controller 106 of the CSD 120. The host may specify a slot number for a CS program 132, a descriptor indicating a data source 204, such as such as FLASH media and a list of LBA ranges, watermarks or buffer thresholds for reading input data from the data source, a descriptor indicating the data destination 206, such as a host memory address(es) and length/ranges (e.g., a scatter/gather list for DMA transfers), watermarks or buffer thresholds for writing output data to the destination, and the like (page 3, paragraph [0026]). However, Jones does not teach or suggest transferring a data, via the interface, from a first memory associated with the host device to a second memory associated with the storage device by an application executing on the host device executing a data operation on the data, wherein the storage device includes a processing element to execute an offload function to accelerate the data operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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August 16, 2026
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