DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7 January 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0220251) in view of Kojima et al. (US 2020/0089414).
In regards to claim 1, Park teaches a memory system (See figure 1), comprising:
a memory (See figure 5) comprising:
a memory cell array (memory cell array 110, figure 5); and
a peripheral circuit (peripheral circuit 120, figure 5) coupled with the memory cell array, the peripheral circuit comprising a page buffer (page buffer circuit 123, figure 5); and
a memory controller (controller 1200, figure 2) coupled with the memory and configured to:
in response to a first read request comprising a first logical address (“The controller may sequentially transmit a read preparing command 00h, the address ADD, and an advanced one-shot read command 42h to the selected memory chip through the input and output lines IO<j:0>.”, paragraph 0064; “In the advanced one-shot read operation, before the sensing operation of the logical pages is completed, a partial sensing operation and an output operation may be simultaneously performed.”, paragraph 0065), read data from the memory cell array (“The memory chip performs the advanced one-shot read operation from a first point in time t1 in response to the advanced one-shot read command 42h.”, paragraph 0065), and store the read data through the page buffer (“When the sensing operation using the first to fifth read voltages R1 to R5 is completed, since a sensing operation of the MSB page of the selected page is completed, MSB data may be stored in the third latches of the page buffers.”, paragraph 0068), wherein the data comprises all data stored in a physical page to which a first physical address corresponding to the first logical address points (“The sensing operation may be performed by sequentially using the first to seventh read voltages R1 to R7. The first to seventh read voltages R1 to R7 may be set in the order in which a lowest voltage level comes first. For example, the first read voltage R1 may be set to be lowest and the seventh read voltage R7 may be set to be highest.”, paragraph 0067; “Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions.”, paragraph 0059); and
in response to a second read request (“The controller may sequentially transmit an LSB setup command 01h and a data output command 3Ah to the memory chip through the input and output lines IO<j:0>.”, paragraph 0079), read data corresponding to a second logical address from the page buffer (“The memory chip may be set such that the LSB data stored in the first latches of the page buffers may be output in response to the LSB setup command 01h.”, paragraph 0079), wherein the second logical address is related to the first logical address (“Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions. For example, the TLC may be programmed into one of an erase status ER and seven program statuses PV1 to PV7. In order to read the TLC including the three logical pages LSB, CSB, and MSB, read operations may be performed on the respective logical pages.”, paragraph 0059).
Park fails to teach that the second read request comprises the second logical address. Kojima teaches that the second read request comprises the second logical address (“In a case where the memory system receives, for example, a read command including a logical address (a sequential read command) sequential to a logical address included in a preceding read command”, paragraph 0025) in order “to accelerate the transfer operation in accordance with the read request” (paragraph 0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Park with Kojima such that the second read request comprises the second logical address in order “to accelerate the transfer operation in accordance with the read request” (id.).
In regards to claim 12, Park teaches a method of operating a memory system, wherein the memory system (See figure 1) comprises a memory (memory device 1100, figure 2) and a memory controller (controller 1200, figure 2) coupled with the memory; the memory comprises a memory cell array (memory cell array 110, figure 5) and a peripheral circuit (peripheral circuit 120, figure 5) coupled with the memory cell array, the peripheral circuit comprising a page buffer (page buffer circuit 123, figure 5); the method comprising:
in response to a first read request comprising a first logical address (“The controller may sequentially transmit a read preparing command 00h, the address ADD, and an advanced one-shot read command 42h to the selected memory chip through the input and output lines IO<j:0>.”, paragraph 0064; “In the advanced one-shot read operation, before the sensing operation of the logical pages is completed, a partial sensing operation and an output operation may be simultaneously performed.”, paragraph 0065), controlling the peripheral circuit to read data stored in the memory cell array (“The memory chip performs the advanced one-shot read operation from a first point in time t1 in response to the advanced one-shot read command 42h.”, paragraph 0065), and storing the read data through the page buffer (“When the sensing operation using the first to fifth read voltages R1 to R5 is completed, since a sensing operation of the MSB page of the selected page is completed, MSB data may be stored in the third latches of the page buffers.”, paragraph 0068), wherein the data comprises all data stored in a physical page to which a first physical address corresponding to the first logical address points (“The sensing operation may be performed by sequentially using the first to seventh read voltages R1 to R7. The first to seventh read voltages R1 to R7 may be set in the order in which a lowest voltage level comes first. For example, the first read voltage R1 may be set to be lowest and the seventh read voltage R7 may be set to be highest.”, paragraph 0067; “Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions.”, paragraph 0059); and
in response to a second read request (“The controller may sequentially transmit an LSB setup command 01h and a data output command 3Ah to the memory chip through the input and output lines IO<j:0>.”, paragraph 0079), controlling the peripheral circuit to read data corresponding to a second logical address in the page buffer (“The memory chip may be set such that the LSB data stored in the first latches of the page buffers may be output in response to the LSB setup command 01h.”, paragraph 0079), wherein the second logical address is related to the first logical address (“Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions. For example, the TLC may be programmed into one of an erase status ER and seven program statuses PV1 to PV7. In order to read the TLC including the three logical pages LSB, CSB, and MSB, read operations may be performed on the respective logical pages.”, paragraph 0059).
Park fails to teach that the second read request comprises the second logical address. Kojima teaches that the second read request comprises the second logical address (“In a case where the memory system receives, for example, a read command including a logical address (a sequential read command) sequential to a logical address included in a preceding read command”, paragraph 0025) in order “to accelerate the transfer operation in accordance with the read request” (paragraph 0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Park with Kojima such that the second read request comprises the second logical address in order “to accelerate the transfer operation in accordance with the read request” (id.).
In regards to claim 20, Park teaches an electronic apparatus, comprising:
a memory system (See figure 1), comprising:
a memory (See figure 5) comprising:
a memory cell array (memory cell array 110, figure 5); and
a peripheral circuit (peripheral circuit 120, figure 5) coupled with the memory cell array, the peripheral circuit comprising a page buffer (page buffer circuit 123, figure 5);
a memory controller (controller 1200, figure 2) coupled with the memory and configured to:
in response to a first read request comprising a first logical address (“The controller may sequentially transmit a read preparing command 00h, the address ADD, and an advanced one-shot read command 42h to the selected memory chip through the input and output lines IO<j:0>.”, paragraph 0064; “In the advanced one-shot read operation, before the sensing operation of the logical pages is completed, a partial sensing operation and an output operation may be simultaneously performed.”, paragraph 0065), read data from the memory cell array (“The memory chip performs the advanced one-shot read operation from a first point in time t1 in response to the advanced one-shot read command 42h.”, paragraph 0065), and store the read data through the page buffer (“When the sensing operation using the first to fifth read voltages R1 to R5 is completed, since a sensing operation of the MSB page of the selected page is completed, MSB data may be stored in the third latches of the page buffers.”, paragraph 0068), wherein the data comprises all data stored in a physical page to which a first physical address corresponding to the first logical address points (“The sensing operation may be performed by sequentially using the first to seventh read voltages R1 to R7. The first to seventh read voltages R1 to R7 may be set in the order in which a lowest voltage level comes first. For example, the first read voltage R1 may be set to be lowest and the seventh read voltage R7 may be set to be highest.”, paragraph 0067; “Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions.”, paragraph 0059); and
in response to a second read request (“The controller may sequentially transmit an LSB setup command 01h and a data output command 3Ah to the memory chip through the input and output lines IO<j:0>.”, paragraph 0079), read data corresponding to a second logical address from the page buffer (“The memory chip may be set such that the LSB data stored in the first latches of the page buffers may be output in response to the LSB setup command 01h.”, paragraph 0079), wherein the second logical address is related to the first logical address (“Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions. For example, the TLC may be programmed into one of an erase status ER and seven program statuses PV1 to PV7. In order to read the TLC including the three logical pages LSB, CSB, and MSB, read operations may be performed on the respective logical pages.”, paragraph 0059); and
a host (host 2000, figure 1) coupled with the memory system.
Park fails to teach that the second read request comprises the second logical address. Kojima teaches that the second read request comprises the second logical address (“In a case where the memory system receives, for example, a read command including a logical address (a sequential read command) sequential to a logical address included in a preceding read command”, paragraph 0025) in order “to accelerate the transfer operation in accordance with the read request” (paragraph 0026). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Park with Kojima such that the second read request comprises the second logical address in order “to accelerate the transfer operation in accordance with the read request” (id.).
In regards to claims 2 and 13, Kojima further teaches that the memory controller is configured to:
in response to the first read request, determine the first physical address corresponding to the first logical address, and send a first read command and the first physical address to the peripheral circuit (“When a read command is received from the host, the buffer determination unit 255 obtains a physical address obtained by logical-physical conversion for a logical address (LBA) included in the read command.”, paragraph 0101); and
in response to the second read request, determine a second physical address corresponding to the second logical address, and send a second read command and the second physical address to the peripheral circuit (“When a read command is received from the host, the buffer determination unit 255 obtains a physical address obtained by logical-physical conversion for a logical address (LBA) included in the read command.”, paragraph 0101).
Park further teaches that the peripheral circuit is configured to:
in response to the first read command and the first physical address (“The memory chip performs the advanced one-shot read operation from a first point in time t1 in response to the advanced one-shot read command 42h.”, paragraph 0065), read data of N logical pages stored in the physical page in the memory cell array to which the first physical address points, wherein N is an integer greater than 1 (“The sensing operation may be performed by sequentially using the first to seventh read voltages R1 to R7.”, paragraph 0067; “Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions.”, paragraph 0059);
latch the data of N logical pages to N first latches of the page buffer respectively (“In accordance with a difference in voltage or current of the bit lines, data of logical pages read from the selected page is stored in the page buffers.”, paragraph 0067; “; and in response to the second read command and the second physical address, read the respective logical page data in the N first latches (“The memory chip may be set such that the LSB data stored in the first latches of the page buffers may be output in response to the LSB setup command 01h.”, paragraph 0079).
In regards to claims 3 and 14, Park further teaches that the N first latches comprise:
(N-1) data latches, each of which configured to: latch data of one logical page in data of (N-1) logical pages in the data of the N logical pages (“Each of the first to ith page buffers PB1 to PBi may include first to mth latches LAT1 to LTm (m is a positive integer) for sensing and storing data. For example, a page buffer for the MLC may have two or more latches, a page buffer for the TLC may have three or more latches, and a page buffer for the QLC may have four or more latches.”, paragraph 0056).
Kojima further teaches that the N first latches comprise:
a cache latch configured to: latch a remaining one of the data of N logical pages (“the XDL 49 functions as an input/output buffer directly electrically connected to the input/output signal line 31b”, paragraph 0072);
the peripheral circuit is configured to:
in response to the second read command and the second physical address (“When a read command or a background read process request is received (S1)”, paragraph 0104), transmit logical page data latched by at least one of the (N-1) data latches to the cache latch (“Consequently, the data stored in the ADL 47 is transferred to and stored in the XDL 49 of the nonvolatile memory 21.”, paragraph 0110), wherein the second read command is configured to indicate reading at least one of the data of (N-1) logical pages (“In the case where the target data is cached in the ADL 47 (‘cache hit’ in S12), the controller 25 further determines whether the target data is cached in the XDL 49 of the nonvolatile memory 21 (S14).”, paragraph 0109); and
control the cache latch to output the logical page data transmitted by the at least one data latch (“Consequently, in the nonvolatile memory 21, data addressed by the data transfer command among the data stored in the XDL 49 is output to the controller 25 via the input/output signal line 31b. The controller 25 transmits the received read data to the host system 10.”, paragraph 0111).
In regards to claims 7 and 18, Kojima further teaches that the memory controller is further configured to:
decide whether the second logical address is related to the first logical address (“Detect sequential read accesses of a plurality of threads and allocate an intermediate buffer (e.g., one of the ADL and the BDL) for each of the threads.”, paragraph 0034); and
in response to the second logical address being related to the first logical address (“Detect sequential read accesses of a plurality of threads and allocate an intermediate buffer (e.g., one of the ADL and the BDL) for each of the threads.”, paragraph 0034), read the data stored in the page buffer that corresponds to the second logical address (“In the case where the target data is cached in the XDL 49 (‘cache hit’ in S14) or after completion of S15, the controller 25 issues a data transfer command (see the data transfer command CM4 illustrated in FIG. 5C) and supplies the data transfer command to the nonvolatile memory 21 (S16). Consequently, in the nonvolatile memory 21, data addressed by the data transfer command among the data stored in the XDL 49 is output to the controller 25 via the input/output signal line 31b. The controller 25 transmits the received read data to the host system 10.”, paragraph 0111).
In regards to claims 8 and 19, Kojima further teaches that the memory controller is further configured to:
decide whether the first read request is a single page read request (“FIG. 11 exemplifies a case where both a data size requested by each read command and a data size instructed by each data transfer command are ¼ (16 KB×¼=4 KB) of a page size in order to simplify the illustration and the description.”, paragraph 0145); and
in response to the first read request being the single page read request (“FIG. 11 exemplifies a case where both a data size requested by each read command and a data size instructed by each data transfer command are ¼ (16 KB×¼=4 KB) of a page size in order to simplify the illustration and the description.”, paragraph 0145), store the read data into the page buffer (“For example, the controller 25 converts a logical address A1 into a physical address (column address C1 and row address R1) for a read command of the thread A, issues a sensing command including designation of the ADL 47 and the row address R1, and supplies the sensing command to the nonvolatile memory 21 (S71).”, paragraph 0146).
In regards to claim 9, Kojima further teaches that the memory controller is configured to:
in response to the first read request being the single page read request (“FIG. 11 exemplifies a case where both a data size requested by each read command and a data size instructed by each data transfer command are ¼ (16 KB×¼=4 KB) of a page size in order to simplify the illustration and the description.”, paragraph 0145), send to the peripheral circuit a command of storing the read data into the page buffer (“For example, the controller 25 converts a logical address A1 into a physical address (column address C1 and row address R1) for a read command of the thread A, issues a sensing command including designation of the ADL 47 and the row address R1, and supplies the sensing command to the nonvolatile memory 21 (S71).”, paragraph 0146).
In regards to claim 10, Kojima further teaches that the memory controller comprises:
a first deciding circuit configured to: decide whether the second logical address is related to the first logical address (“In a case where the memory system receives, for example, a read command including a logical address (a sequential read command) sequential to a logical address included in a preceding read command”, paragraph 0025); and
a second deciding circuit configured to: decide whether the first read command is the single page read request (“FIG. 11 exemplifies a case where both a data size requested by each read command and a data size instructed by each data transfer command are ¼ (16 KB×¼=4 KB) of a page size in order to simplify the illustration and the description.”, paragraph 0145).
In regards to claim 11, Park further teaches that the second logical address being related to the first logical address comprises:
the first physical address and a second physical address corresponding to the second logical address point to the same physical page (“The sensing operation may be performed by sequentially using the first to seventh read voltages R1 to R7. The first to seventh read voltages R1 to R7 may be set in the order in which a lowest voltage level comes first. For example, the first read voltage R1 may be set to be lowest and the seventh read voltage R7 may be set to be highest.”, paragraph 0067; “Referring to FIG. 8, the TLC may include three logical pages, which are the LSB, CSB, and MSB pages. The three logical pages of the TLC may have eight threshold voltage distributions. For example, the TLC may be programmed into one of an erase status ER and seven program statuses PV1 to PV7. In order to read the TLC including the three logical pages LSB, CSB, and MSB, read operations may be performed on the respective logical pages.”, paragraph 0059).
Claims 4-6 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0220251) in view of Kojima et al. (US 2020/0089414) and Lee (US 2019/0267073).
In regards to claims 4 and 15, Park in view of Kojima teaches claims 3 and 14. Park in view of Kojima fails to teach that the peripheral circuit is further configured to:
after transmitting the logical page data latched by the at least one data latch to the cache latch, reset the at least one data latch.
Lee teaches that the peripheral circuit is further configured to:
after transmitting the logical page data latched by the at least one data latch to the cache latch, reset the at least one data latch (“When the page data is transferred from the page buffer 130 to the cache buffer 160, the page buffer 130 is reset to read a next page.”, paragraph 0109)
in order “to read a next page” (id.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Park with Kojima and Lee such that the peripheral circuit is further configured to:
after transmitting the logical page data latched by the at least one data latch to the cache latch, reset the at least one data latch
in order “to read a next page” (id.).
In regards to claims 5 and 16, Kojima further teaches that the page buffer further comprises a second latch (intermediate buffer (BDL) 48, figure 3);
the peripheral circuit is further configured to:
before transmitting the logical page data latched by the at least one data latch to the cache latch, control the cache latch to transmit the latched remaining data of one logical page to the second latch (“In the case where the target data is not cached in the BDL 48 (‘cache miss’ in S17), the controller 25 issues a sensing command including designation of the BDL 48 (see the sensing command CM2 illustrated in FIG. 5B) and supplies the sensing command to the nonvolatile memory 21 (S18). Consequently, the data read through the sensing operation from a memory cell addressed by the sensing command is stored in the BDL 48 of the nonvolatile memory 21.”, paragraph 0112).
Lee further teaches that the peripheral circuit is further configured to:
reset the cache latch (“Subsequently, the cache buffer 160 and the page buffer 130 may be reset.”, paragraph 0126).
In regards to claims 6 and 17, Kojima further teaches that the peripheral circuit is further configured to:
after resetting the at least one data latch, transmit the remaining data of one logical page latched by the second latch to the data latch (“In a case where the target data is not cached in the XDL 49 (‘cache miss’ in S19), or after completion of S18, the controller 25 issues an inter-latch transfer command including designation of the BDL 48 (see the inter-latch transfer command CM5 illustrated in FIG. 5D) and supplies the inter-latch transfer command to the nonvolatile memory 21 (S20). Consequently, the data stored in the BDL 48 is transferred to and stored in the XDL 49 of the nonvolatile memory 21.”, paragraph 0114).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US 2015/0378887) teaches dumping page data into data latches. Nagadomi (US 2016/0365154) teaches reading upper and lower pages. Kifune (US 2017/0011795) teaches sequentially stepping read voltages and storing data in various latch circuits. Bang (US 2019/0214094) teaches a multi-sensing manager controlling a page buffer. Maejima (US 2019/0295657) teaches reading based on size of data. Yang (US 10,650,896) teaches using a pre-read operation when programming data. Harada (US 2023/0021244) teaches reading using all read voltages. Harada (US 2025/0036310) teaches reading adjacent addresses using normal reads and cache reads. He (US 2025/0174279) teaches a plurality of latch circuits.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 17 February 2026