DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sherman (US Patent No. 5535090) in view of Watanabe et al (US Patent No. 5625526).
Regarding claim 1, Sherman discloses an electrostatic chuck (i.e., such as electrostatic chuck 8; see for example fig. 1, Col. 5 lines 57+) comprising: a dielectric substrate (i.e., dielectric substrate 22; see for example fig. 1, Col. 5 lines 57+) including a placement surface (i.e., such as placement surface A, B; see for example fig. 1, Col. 5 lines 57+) on which an object (i.e., such as object 10; see for example fig. 1, Col. 5 lines 57+) to be attracted (i.e., such as attracting object 10; see for example fig. 1, Col. 5 lines 57+) is placed (i.e., such as placing object 10; see for example fig. 1, Col. 5 lines 57+); an internal electrode (i.e., such as internal electrode 23; see for example fig. 1, Col. 5 lines 57+) provided inside (i.e., such as 23 is provided inside 8 between 22 and 24; see for example fig. 1, Col. 5 lines 57+) the dielectric substrate (i.e., dielectric substrate 22; see for example fig. 1, Col. 5 lines 57+); a base plate (i.e., such as base plate 4; see for example fig. 1, Col. 5 lines 57+) made of a metal (i.e., such as metal base plate 4; see for example fig. 1, Col. 5 lines 57+) and joined (i.e., such as 4 is joined to 22 via 24; see for example fig. 1, Col. 5 lines 57+) to the dielectric substrate (i.e., dielectric substrate 22; see for example fig. 1, Col. 5 lines 57+); and a conductive member (i.e., such as conductive member 20; see for example fig. 1, Col. 5 lines 57+) configured (i.e., such as 20 is configured to electrically connect 23 to 4; see for example fig. 1, Col. 5 lines 57+) to electrically connect (i.e., such as 20 is configured to electrically connect 23 to 4; see for example fig. 1, Col. 5 lines 57+) the internal electrode (i.e., such as internal electrode 23; see for example fig. 1, Col. 5 lines 57+) and the base plate (i.e., such as base plate 4; see for example fig. 1, Col. 5 lines 57+) to each other (i.e., such as each of 23 and the other 4 are electrically connected via 20; see for example fig. 1, Col. 5 lines 57+).
Sherman does not explicitly disclose wherein a first recessed section which accommodates a part of the conductive member is formed in a surface on a base plate side of the dielectric substrate, a second recessed section which accommodates a part of the conductive member is formed in a surface on a dielectric substrate side of the base plate, and when viewed from a direction perpendicular to the placement surface, the first recessed section is larger than the second recessed section.
Watanabe discloses an ESC (i.e., see for example fig. 11, Col. 10 lines 52+); wherein a first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+) which accommodates (i.e., such as 138 accommodates the upper portion of 180 within susceptor 6; see for example fig. 11, Col. 10 lines 52+) a part (i.e., such as part upper portion of 180; see for example fig. 11, Col. 10 lines 52+) of the conductive member (i.e., such as the conductive member 180; see for example fig. 11, Col. 10 lines 52+) is formed in a surface (i.e., such as surface top face of base 94/bottom face of susceptor 6; see for example fig. 11, Col. 10 lines 52+) on a base plate side (i.e., such as the top-face side of base plate 94; see for example fig. 11, Col. 10 lines 52+) of the dielectric substrate (i.e., such as the dielectric substrate 6; see for example fig. 11, Col. 10 lines 52+), a second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+) which accommodates (i.e., such as 116 accommodates the lower portion of 180 within base 94; see for example fig. 11, Col. 10 lines 52+) a part (i.e., such as part lower portion of 180; see for example fig. 11, Col. 10 lines 52+) of the conductive member (i.e., such as the conductive member 180; see for example fig. 11, Col. 10 lines 52+) is formed in a surface (i.e., such as surface top face of base 94/bottom face of susceptor 6; see for example fig. 11, Col. 10 lines 52+) on a dielectric substrate side (i.e., such as the bottom-face side of dielectric substrate susceptor 6; see for example fig. 11, Col. 10 lines 52+) of the base plate (i.e., such as the base plate 94; see for example fig. 11, Col. 10 lines 52+), and when viewed (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) from a direction (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) perpendicular (i.e., such as Y-axis is perpendicular to X-axis and Z-axis; see for example fig. 11, Col. 10 lines 52+) to the placement surface (i.e., such as the placement surface top-face of susceptor 6 on the X-axis; see for example fig. 11, Col. 10 lines 52+), the first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+) is larger than (i.e., such as the width/diameter of numeral 182 within the boundary of 182A side is larger than the width/diameter of numeral 182 within the boundary of 116 side, in other words, wall 116 is relatively tucked in to wall 182A with respect to the whole circumference of the imaginary cylinder numeral 182; see for example fig. 11, Col. 10 lines 52+) the second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the recess sections in Sherman, as taught by Watanabe, as it provides the advantage of optimizing the circuit design towards preventing electrical arcing, reducing thermal/mechanical stress, and accommodating thermal expansion inside high-power semiconductor processing chambers.
Regarding claim 2, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Watanabe further discloses the ESC (i.e., see for example fig. 11, Col. 10 lines 52+); wherein when viewed (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) from the direction (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) perpendicular (i.e., such as Y-axis is perpendicular to X-axis and Z-axis; see for example fig. 11, Col. 10 lines 52+) to the placement surface (i.e., such as the placement surface top-face of susceptor 6 on the X-axis; see for example fig. 11, Col. 10 lines 52+), an inner circumferential surface (i.e., such as inner circumferential surface 182A; see for example fig. 11, Col. 10 lines 52+) of the first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+) is on an outer side (i.e., such as wall of numeral 182A is the outer wall with respect to the inner wall of numeral 116; see for example fig. 11, Col. 10 lines 52+) relative (i.e., such as the width/diameter of numeral 182 within the boundary of 182A side is larger than the width/diameter of numeral 182 within the boundary of 116 side, in other words, wall 116 is relatively tucked in to wall 182A with respect to the whole circumference of the imaginary cylinder numeral 182; see for example fig. 11, Col. 10 lines 52+) to an inner circumferential surface (i.e., such as wall of numeral 116 is the inner wall with respect to the outer wall of numeral 182A; see for example fig. 11, Col. 10 lines 52+) of the second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+) over a whole circumference (i.e., such as whole circumference 182; for instance, the width/diameter of numeral 182 within the boundary of 182A side is larger than the width/diameter of numeral 182 within the boundary of 116 side, in other words, wall 116 is relatively tucked in to wall 182A with respect to the whole circumference of the imaginary cylinder numeral 182; see for example fig. 11, Col. 10 lines 52+).
Regarding claim 3, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Watanabe further discloses the ESC (i.e., see for example fig. 11, Col. 10 lines 52+); wherein when viewed (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) from the direction (i.e., such as view in direction Y-axis; see for example fig. 11, Col. 10 lines 52+) perpendicular (i.e., such as Y-axis is perpendicular to X-axis and Z-axis; see for example fig. 11, Col. 10 lines 52+) to the placement surface (i.e., such as the placement surface top-face of susceptor 6 on the X-axis; see for example fig. 11, Col. 10 lines 52+), a diameter (i.e., such as width/diameter of pin 180; see for example fig. 11, Col. 10 lines 52+) of the part (i.e., such as part upper portion of 180; see for example fig. 11, Col. 10 lines 52+) of the conductive member (i.e., such as the conductive member 180; see for example fig. 11, Col. 10 lines 52+) accommodated (i.e., such as 138 accommodates the upper portion of 180 within susceptor 6; see for example fig. 11, Col. 10 lines 52+) in the first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+) is equal (i.e., such as equal as uniformed solid one piece pin 180; see for example fig. 11, Col. 10 lines 52+) to a diameter (i.e., such as width/diameter of pin 180; see for example fig. 11, Col. 10 lines 52+) of the part (i.e., such as part lower portion of 180; see for example fig. 11, Col. 10 lines 52+) of the conductive member (i.e., such as the conductive member 180; see for example fig. 11, Col. 10 lines 52+) accommodated (i.e., such as 116 accommodates the lower portion of 180 within base 94; see for example fig. 11, Col. 10 lines 52+) in the second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+).
Regarding claim 5, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Sherman further discloses the electrostatic chuck (i.e., such as electrostatic chuck 8; see for example fig. 1, Col. 5 lines 57+); further comprising: a joining layer (i.e., such as joining layer 24; see for example fig. 1, Col. 5 lines 57+) between the base plate (i.e., such as base plate 4; see for example fig. 1, Col. 5 lines 57+) and the dielectric substrate (i.e., dielectric substrate 22; see for example fig. 1, Col. 5 lines 57+); and a blocking section (i.e., such as blocking section 21; see for example fig. 1, Col. 5 lines 57+) between the base plate (i.e., such as base plate 4; see for example fig. 1, Col. 5 lines 57+) and the dielectric substrate (i.e., dielectric substrate 22; see for example fig. 1, Col. 5 lines 57+), the conductive member (i.e., such as conductive member 20; see for example fig. 1, Col. 5 lines 57+) being spaced (i.e., such as 20 is spaced by the width of 21; see for example fig. 1, Col. 5 lines 57+) from the joining layer (i.e., such as joining layer 24; see for example fig. 1, Col. 5 lines 57+) by the blocking section (i.e., such as blocking section 21; see for example fig. 1, Col. 5 lines 57+).
Regarding claim 6, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Watanabe further discloses the ESC (i.e., see for example fig. 11, Col. 10 lines 52+); wherein the first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+) and the second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+) are circular (i.e., such as circular/imaginary cylinder 182; see for example fig. 11, Col. 10 lines 52+), and the second recessed section (i.e., such as second recessed section 116; see for example fig. 11, Col. 10 lines 52+) has a smaller diameter (i.e., such as the width/diameter of numeral 182 within the boundary of 116 side is smaller than the width/diameter of numeral 182 within the boundary of 182A side, in other words, wall 116 is relatively tucked in to wall 182A with respect to the whole circumference of the imaginary cylinder numeral 182; see for example fig. 11, Col. 10 lines 52+) than the first recessed section (i.e., such as first recessed section 138; see for example fig. 11, Col. 10 lines 52+).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sherman (US Patent No. 5535090) in view of Watanabe et al (US Patent No. 5625526) and further in view of Yoshikawa et al (US Publication No. 20190385883).
Regarding claim 4, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Neither Sherman nor Watanabe explicitly discloses further comprising: a plate on the conductive member; and a plurality of via sections extending from the plate and to the internal electrode.
Yoshikawa discloses an ESC (i.e., see for example fig. 3, para. [0028]- [0042]); wherein further comprising: a plate (i.e., such as plate 162; see for example fig. 3, para. [0028]- [0042]) on the conductive member (i.e., such as the conductive member 191; see for example fig. 3, para. [0028]- [0042]) and a plurality of via sections extending (i.e., such as plurality of via sections extending 163; see for example fig. 3, para. [0028]- [0042]) from the plate (i.e., such as plate 162; see for example fig. 3, para. [0028]- [0042]) and to the internal electrode (i.e., such as the internal electrode 164; see for example fig. 3, para. [0028]- [0042]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included plate-via-extension in Sherman, as taught by Yoshikawa, as it provides the advantage of optimizing the circuit design towards uniform electrical distribution, superior thermal management, and mechanical stability during high-stress semiconductor processes such as etching and CVD.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sherman (US Patent No. 5535090) in view of Watanabe et al (US Patent No. 5625526) and further in view of Okugawa et al (US Publication No. 20160126125).
Regarding claim 7, Sherman in view of Watanabe and the teachings of Sherman as modified by Watanabe have been discussed above.
Neither Sherman nor Watanabe explicitly discloses further comprising: another internal electrode provided inside the dielectric substrate, the another internal electrode being spaced from the surface on the base plate side of the dielectric substrate by the internal electrode.
Okugawa discloses an ESC (i.e., see for example fig. 1, para. [0044]- [0056]); wherein further comprising: another internal electrode (i.e., such as another internal electrode 21; see for example fig. 1, para. [0044]- [0056]) provided inside (i.e., such as 21 is provided inside 11; see for example fig. 1, para. [0044]- [0056]) the dielectric substrate (i.e., such as the dielectric substrate 11; see for example fig. 1, para. [0044]- [0056]), the another internal electrode (i.e., such as another internal electrode 21; see for example fig. 1, para. [0044]- [0056]) being spaced (i.e., such as 21 is spaced from 112/121 via 41; see for example fig. 1, para. [0044]- [0056]) from the surface (i.e., such as the surface 112/121; see for example fig. 1, para. [0044]- [0056]) on the base plate side (i.e., such as the side 121 of the base plate 12; see for example fig. 1, para. [0044]- [0056]) of the dielectric substrate (i.e., such as the dielectric substrate 11; see for example fig. 1, para. [0044]- [0056]) by the internal electrode (i.e., such as the internal electrode 41; see for example fig. 1, para. [0044]- [0056]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the second electrode in Sherman, as taught by Okugawa, as it provides the advantage of optimizing the circuit design towards allowing precise, localized control over the substrate.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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