DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US PGPUB 2018/0122485) in view of Fujimoto (US PGPUB 2004/0169738; hereinafter “Fujimoto ‘738”).
With regard to Claim 1, Park teaches a memory device comprising:
a memory cell array comprising a plurality of memory cells ([0027] “Referring to FIG. 1, a nonvolatile memory device 100 may include a memory cell array 110.”); and
a control logic configured to control a memory operation with respect to the memory cell array, based on a command and an address provided from a memory controller outside the memory device ([0039] “The control logic 140 may be connected to the address decoder 120 and the page buffer circuit 130. The control logic 140 may be configured to control overall operations of the nonvolatile memory device 100. The control logic 140 may operate in response to a command CMD transmitted from the outside.”),
wherein the control logic is configured to:
during a [memory operation], generate noise detection data based on detecting whether noise occurs in power provided to the memory device, wherein the memory device is configured to, during the [memory operation], communicate operation data corresponding to the command and the address ([0062] “FIG. 6 is a flowchart illustrating an operating method of a nonvolatile memory device using power noise detection, according to an example embodiment of the inventive concepts. Referring to FIG. 6, the nonvolatile memory device 100 may perform an operation including at least one period. The operation may include a read operation, a program operation, an erase operation, etc.” [0063] “In operation S105, the nonvolatile memory device 100 may perform a first period of the operation. In operation S110, the nonvolatile memory device 100 may determine whether a strong power noise is detected during the first period.”), and
transfer the noise detection data to the memory controller ([0109] “The power noise detection result may be sent to the memory controller 1100.”).
With further regard to claim 1, Park does not teach the noise being detected during a DMA operation as described in claim 1. Fujimoto ‘738 teaches
during a direct memory access (DMA) operation, detecting whether noise occurs ([0007] “a direct memory access (DMA) transfer method is ordinarily used to write an AD-converted signal to a RAM with efficiency.” [0020] “In the case where the digital signal is written to the RAM by using the above-mentioned DMA transfer system, electric power change noise at the time of DMA transfer is mixed in the analog signal from the image pickup device. In particular, noise is mixed in certain portions in each image line to form noticeable vertical streaks since the DMA transfer timing is generally constant with respect to each line of the image pickup device.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Park with the noise being detected during a DMA operation as taught by Fujimoto ‘738 in order “to avoid or reduce the influence of noise” (Fujimoto ‘738 [0021]).
With regard to claim 4, Park in view of Fujimoto ‘738 teaches all the limitations of claim 1 as described above. Park further teaches wherein the memory device is configured to receive the command and the address from the memory controller through a first bus, and transmit and receive the operation data to and from the memory controller through a second bus ([0028] “The memory cell array 110 may be connected to the address decoder 120 and the page buffer circuit 130. For example, the memory cell array 110 may be connected to the address decoder 120 through string selection lines SSL, word lines WL, and ground selection lines GSL. Meanwhile, the memory cell array 110 may be connected to the page buffer circuit 130 through hit lines BL.”).
With regard to claim 5, Park in view of Fujimoto ‘738 teaches all the limitations of claim 4 as described above. Park further teaches wherein the control logic is configured to transfer the noise detection data to the memory controller through the first bus ([0059] “FIG. 5 is a block diagram illustrating OR logics for indicating whether power noises are generated, according to an example embodiment of the inventive concepts. Referring to FIG. 5, the control logic 140 may include first and second OR logics 143a and 143b. Status registers STAT_RG1 and STAT_RG2 may be included in the register unit 142,” wherein the “STAT_SPN” shown in Fig. 5 is one type of bus.).
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Fujimoto ‘738 as applied to Claim 1 above, and further in view of Seo et al. (US PGPUB 2022/0276802).
With regard to claim 2, Park in view of Fujimoto ‘738 teaches all the limitations of claim 1 as described above. Park in view of Fujimoto ‘738 does not teach the get feature command as described in claim 2. Seo teaches
wherein the memory device is configured to transfer the noise detection data in response to a get feature command ([0066] “The OVS circuit 155 may output the stored detection information OVSDI to the memory controller 200. For example, the detection information OVSDI may be output using UIB out or output in response to a special command, e.g., a get feature command, a status read command, or the like.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Park in view of Fujimoto ‘738 with the get feature command as taught by Seo since “variation of the threshold voltage distribution may cause an error (e.g., error correction is impossible)” (Seo [0031]) and the transferring of the “noise detection data” may aid in correcting any related errors.
With regard to claim 9, Park in view of Fujimoto ‘738 teaches all the limitations of claim 1 as described above. Park in view of Fujimoto ‘738 does not teach the get feature command as described in claim 9. Seo teaches further comprising:
a latch circuit configured to store the noise detection data, wherein the latch circuit is configured to transfer the noise detection data to the memory controller in response to a get feature command ([0063] “the input/output buffer circuit 140 may output data sensed and latched by the page buffer circuit 130 externally.” [0065] “the OVS circuit 155 may control the plurality of page buffers PB1 to PBn to store sensing data corresponding to each of the plurality of sensing results in a plurality of latch sets provided in the plurality of page buffers PB1 to PBn,” [0066] “The OVS circuit 155 may output the stored detection information OVSDI to the memory controller 200. For example, the detection information OVSDI may be output using UIB out or output in response to a special command, e.g., a get feature command, a status read command, or the like.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Park in view of Fujimoto ‘738 with the get feature command as taught by Seo since “variation of the threshold voltage distribution may cause an error (e.g., error correction is impossible)” (Seo [0031]) and the transferring of the “noise detection data” may aid in correcting any related errors.
Claims 10, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim et al. (US PGPUB 2017/0110165) and Fujimoto ‘738.
With regard to Claim 10, Park teaches a memory controller controlling a memory device, the memory controller comprising:
a memory interface (Fig. 10: NVM Interface 1160);
an operation processor (Fig. 10: CPU 1110) configured to:
receive noise detection data indicating whether noise occurs in power provided to the memory device through the first bus during a [memory operation] ([0062] “FIG. 6 is a flowchart illustrating an operating method of a nonvolatile memory device using power noise detection, according to an example embodiment of the inventive concepts. Referring to FIG. 6, the nonvolatile memory device 100 may perform an operation including at least one period. The operation may include a read operation, a program operation, an erase operation, etc.” [0063] “In operation S105, the nonvolatile memory device 100 may perform a first period of the operation. In operation S110, the nonvolatile memory device 100 may determine whether a strong power noise is detected during the first period.” [0109] “The power noise detection result may be sent to the memory controller 1100.”); and
perform the [memory operation] based on the noise being detected in the power during the [memory operation] according to the noise detection data ([0080] “FIG. 8 is a flowchart illustrating a program operation of a nonvolatile memory device, according to an example embodiment of the inventive concepts. Referring to FIG. 8, when the nonvolatile memory device 100 detects a power noise in a program execution period, the nonvolatile memory device 100 may again perform the program execution period after adjusting an ISPP setting and a program time setting. Also, if the strong power noise is detected in all operation periods, the nonvolatile memory device 100 may perform a recovery period of the program operation immediately.”).
With further regard to claim 10, Park does not teach the first and second bus as described in claim 10. Kim teaches the memory interface configured to:
transfer a command and an address through a first bus to control a memory operation on the memory device ([0037] “a command and an address may be transmitted as a command/address signal CA to the memory device 100 from the memory controller 200 through a command/address bus 11.”), and
transmit and receive operation data corresponding to the command and the address to and from the memory device through a second bus ([0037] “A data signal (or data) DQ may be transmitted to the memory device 100 from the memory controller 200 or may be transmitted to the memory controller 200 from the memory device 100, through a data bus 17 including bi-directional signal lines.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Park with the first and second bus as taught by Kim “in order to reduce the number of signal lines between the memory device 100 and the memory controller 200” (Kim [0037]).
With further regard to claim 10, Park in view of Kim does not teach performing the DMA operation based on the detected noise as described in claim 10. Fujimoto ‘738 teaches
wherein the [memory operation] is a direct memory access (DMA) operation ([0007] “a direct memory access (DMA) transfer method is ordinarily used to write an AD-converted signal to a RAM with efficiency.”); and
noise being detected in the power during the DMA operation ([0020] “In the case where the digital signal is written to the RAM by using the above-mentioned DMA transfer system, electric power change noise at the time of DMA transfer is mixed in the analog signal from the image pickup device. In particular, noise is mixed in certain portions in each image line to form noticeable vertical streaks since the DMA transfer timing is generally constant with respect to each line of the image pickup device.” [0012] “when the frequency of the basic operating clock is high, noise is mixed through the entire portion of the analog signal corresponding to one pixel. At the time of AD conversion of a still image output, therefore, the frequency of the basic operating clock is reduced to enable sampling of a low-noise portion or a portion in which noise is sufficiently attenuated in the analog signal for each pixel in which noise is mixed, and AD conversion of the sampled portion.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Park in view of Kim with the noise being detected during a DMA operation as taught by Fujimoto ‘738 in order “to avoid or reduce the influence of noise” (Fujimoto ‘738 [0021]).
With regard to claim 16, Park in view of Kim and Fujimoto ‘738 teaches all the limitations of claim 10 as described above. Park further teaches wherein the operation processor is configured to:
based on a bit value of the noise detection data being a first value, determine that the noise has been detected in the power during the [memory operation], and based on the bit value of the noise detection data being a second value, determine that the noise has not been detected in the power during the [memory operation] ([0063] “In operation S105, the nonvolatile memory device 100 may perform a first period of the operation. In operation S110, the nonvolatile memory device 100 may determine whether a strong power noise is detected during the first period.” [0059] “FIG. 5 is a block diagram illustrating OR logics for indicating whether power noises are generated... Referring to FIG. 5, the control logic 140 may include first and second OR logics 143a and 143b. Status registers STAT_RG1 and STAT_RG2 may be included in the register unit 142.” [0060] “If the first OR logic 143a receives at least one of the strong power noise signal VDD_SPN, the strong ground noise signal GND_SPN, and the strong external noise signal eVPP_SPN, the first OR logic 143a may output a strong noise status signal STAT SPN to the first status register STAT_RG1,” wherein the “STAT_RG1” register includes a “bit value” which indicates whether or not power noise has been detected.).
With further regard to claim 16, Park in view of Kim does not teach the DMA operation as described in claim 16. Fujimoto ‘738 teaches
wherein the [memory operation] is a direct memory access (DMA) operation ([0007] “a direct memory access (DMA) transfer method is ordinarily used to write an AD-converted signal to a RAM with efficiency.” [0020] “In the case where the digital signal is written to the RAM by using the above-mentioned DMA transfer system, electric power change noise at the time of DMA transfer is mixed in the analog signal from the image pickup device. In particular, noise is mixed in certain portions in each image line to form noticeable vertical streaks since the DMA transfer timing is generally constant with respect to each line of the image pickup device.”).
With regard to Claim 18, Park teaches an operating method of a memory system comprising a memory controller and a memory device, the operating method comprising:
generating, by the memory device, noise detection data by detecting whether noise occurs in power provided to the memory device during the DMA operation ([0062] “FIG. 6 is a flowchart illustrating an operating method of a nonvolatile memory device using power noise detection, according to an example embodiment of the inventive concepts. Referring to FIG. 6, the nonvolatile memory device 100 may perform an operation including at least one period. The operation may include a read operation, a program operation, an erase operation, etc.” [0063] “In operation S105, the nonvolatile memory device 100 may perform a first period of the operation. In operation S110, the nonvolatile memory device 100 may determine whether a strong power noise is detected during the first period.”);
transmitting, by the memory device, the noise detection data to the memory controller through the first bus ([0109] “The power noise detection result may be sent to the memory controller 1100.”); and
determining, by the memory controller, whether the noise is detected based on the noise detection data, and performing the [memory operation] based on the noise being detected in the power ([0080] “FIG. 8 is a flowchart illustrating a program operation of a nonvolatile memory device, according to an example embodiment of the inventive concepts. Referring to FIG. 8, when the nonvolatile memory device 100 detects a power noise in a program execution period, the nonvolatile memory device 100 may again perform the program execution period after adjusting an ISPP setting and a program time setting. Also, if the strong power noise is detected in all operation periods, the nonvolatile memory device 100 may perform a recovery period of the program operation immediately.”).
With further regard to claim 18, Park does not teach the first and second bus as described in claim 18. Kim teaches:
transmitting, by the memory controller, a command and an address through a first bus to control a memory operation on the memory device ([0037] “a command and an address may be transmitted as a command/address signal CA to the memory device 100 from the memory controller 200 through a command/address bus 11.”), and
performing, by the memory controller, a [memory operation] in which operation data corresponding to the command and the address is transmitted and received through a second bus ([0037] “A data signal (or data) DQ may be transmitted to the memory device 100 from the memory controller 200 or may be transmitted to the memory controller 200 from the memory device 100, through a data bus 17 including bi-directional signal lines.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Park with the first and second bus as taught by Kim “in order to reduce the number of signal lines between the memory device 100 and the memory controller 200” (Kim [0037]).
With further regard to claim 18, Park in view of Kim does not teach performing the DMA operation based on the detected noise as described in claim 10. Fujimoto ‘738 teaches
wherein the [memory operation] is a direct memory access (DMA) operation ([0007] “a direct memory access (DMA) transfer method is ordinarily used to write an AD-converted signal to a RAM with efficiency.”); and
performing, by the memory controller, a direct memory access (DMA) operation, and noise being detected in the power ([0020] “In the case where the digital signal is written to the RAM by using the above-mentioned DMA transfer system, electric power change noise at the time of DMA transfer is mixed in the analog signal from the image pickup device. In particular, noise is mixed in certain portions in each image line to form noticeable vertical streaks since the DMA transfer timing is generally constant with respect to each line of the image pickup device.” [0012] “when the frequency of the basic operating clock is high, noise is mixed through the entire portion of the analog signal corresponding to one pixel. At the time of AD conversion of a still image output, therefore, the frequency of the basic operating clock is reduced to enable sampling of a low-noise portion or a portion in which noise is sufficiently attenuated in the analog signal for each pixel in which noise is mixed, and AD conversion of the sampled portion.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Park in view of Kim with the noise being detected during a DMA operation as taught by Fujimoto ‘738 in order “to avoid or reduce the influence of noise” (Fujimoto ‘738 [0021]).
Claims 11 and 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Fujimoto ‘738 as applied to Claims 10 and 18 above, and further in view of Seo.
With regard to claim 11, Park in view of Kim and Fujimoto ‘738 teaches all the limitations of claim 10 as described above. Park in view of Kim and Fujimoto ‘738 does not teach the get feature command as described in claim 11. Seo teaches
wherein the operation processor is configured to transmit a get feature command through the first bus, and receive the noise detection data in response to the get feature command ([0066] “The OVS circuit 155 may output the stored detection information OVSDI to the memory controller 200. For example, the detection information OVSDI may be output using UIB out or output in response to a special command, e.g., a get feature command, a status read command, or the like,” wherein the “get feature” command would be transmitted via the “command/address bus 11”, i.e. “first bus”, as taught by Kim, since it is a type of command.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Park in view of Kim and Fujimoto ‘738 with the get feature command as taught by Seo since “variation of the threshold voltage distribution may cause an error (e.g., error correction is impossible)” (Seo [0031]) and the transferring of the “noise detection data” may aid in correcting any related errors.
With regard to claim 19, Park in view of Kim and Fujimoto ‘738 teaches all the limitations of claim 18 as described above. Park in view of Kim and Fujimoto ‘738 does not teach the get feature command as described in claim 19. Seo teaches further comprising:
wherein transmitting the noise detection data to the memory controller includes storing the noise detection data in a latch circuit inside the memory device; and transferring the noise detection data to the memory controller in response to a get feature command from the memory controller ([0063] “the input/output buffer circuit 140 may output data sensed and latched by the page buffer circuit 130 externally.” [0065] “the OVS circuit 155 may control the plurality of page buffers PB1 to PBn to store sensing data corresponding to each of the plurality of sensing results in a plurality of latch sets provided in the plurality of page buffers PB1 to PBn,” [0066] “The OVS circuit 155 may output the stored detection information OVSDI to the memory controller 200. For example, the detection information OVSDI may be output using UIB out or output in response to a special command, e.g., a get feature command, a status read command, or the like.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Park in view of Kim and Fujimoto ‘738 with the get feature command as taught by Seo since “variation of the threshold voltage distribution may cause an error (e.g., error correction is impossible)” (Seo [0031]) and the transferring of the “noise detection data” may aid in correcting any related errors.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Fujimoto ‘738 as applied to Claim 10 above, and further in view of Fujimoto (US PGPUB 2012/0079338; hereinafter “Fujimoto ‘338”).
With regard to claim 15, Park in view of Kim and Fujimoto ‘738 teaches all the limitations of claim 10 as described above. Park in view of Kim and Fujimoto ‘738 does not teach the stopping of the command as described in claim 15. Fujimoto ‘338 teaches
wherein the operation processor is configured to stop applying the command through the first bus during a period in which the DMA operation is performed again ([0014] “If a certain error including a bit error occurs by checking by CRC code etc. when using a conventional command protocol, a host must temporarily stop transfer by an abort command and retry the command. This interrupts data transfer and decreases the transfer efficiency. Especially when interruption by noise like this occurs during direct memory access (DMA) transfer using hardware, processing by a driver is necessary, and the effect of DMA decreases.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Park in view of Fujimoto ‘738 with the stopping of the command as taught by Kim and Fujimoto ‘338 since “if a bit error occurs because of noise during data transfer by checking by CRC code etc., a host must interrupt the data transfer once and then retry the data transfer” (Fujimoto ‘338 [0015]).
Allowable Subject Matter
Claims 3, 6-8, 12-14, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The above mentioned claims have been indicated as reciting allowable subject matter due to the inclusion of a novel method and system for detecting and managing power noise during a DMA operation. The prior art references teach various methods and systems for detecting and managing power noise, but nowhere does any of the prior art disclose a method or system for detecting and managing power noise which includes the specific set of steps disclosed in Applicant’s dependent Claims 3, 6-8, 12-14, 17 and 20, particularly with regard to the claim limitations which recite:
Claim 3: “wherein the control logic is configured to receive the get feature command within a DMA operation period.”
Claim 6: “wherein the control logic is configured to obtain a reference value corresponding to the DMA operation based on DMA information indicating information about the DMA operation.”
Claim 12: “wherein the operation processor is configured to transmit the get feature command within a DMA operation period.”
Claim 13: “the operation processor is configured to perform the first DMA operation through the second bus based on the noise being detected in the power during the first DMA operation.”
Claim 14: “the operation processor is configured to perform the second DMA operation through the second bus based on the noise being detected in the power during the second DMA operation.”
Claim 17: “the operation processor is configured to determine whether the noise has been detected in the power during the first DMA operation based on a bit value of a first bit of the noise detection data, and
determine whether the noise has been detected in the power during the second DMA operation based on a bit value of a second bit of the noise detection data.”
Claim 20: “performing the DMA operation includes,
performing the first DMA operation through the second bus, based on the noise being detected in the power during the first DMA operation; and
performing the second DMA operation through the second bus, based on the noise being detected in the power during the second DMA operation.”
The corresponding dependent Claims 7-8 further limit Claims 6, and thus recite allowable subject matter by virtue of their dependency.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Liu et al. (US PGPUB 2004/0066208) discloses a method and apparatus for on-die noise detection that includes one more voltage noise sensors and one or more associated comparators, wherein the noise sensors monitor the power supply and ground voltage levels to detect differences or changes between the two levels.
However, none of the prior art teaches detecting and managing power noise in the same manner as described by Applicant’s Independent Claims, particularly with regard to the limitations which indicated above.
Conclusion
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 January 27, 2026