DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a Non-Final Office Action in response to communications received on January 7, 2025. Claims 1-20 are pending and addressed below.
Specification
For the record, Examiner acknowledges that the Specification submitted on January 7, 2025 has been accepted.
Drawings
For the record, Examiner acknowledges that the Drawings submitted on January 7, 2025 have been accepted.
Claim Objections
Claims 8 and 15 objected to because of the following informalities: Claim 8 recites the phrase “the cryptographical operations” (plural) where the claim previously recites a “cryptographic operation” (singular). It is suggested the phrase be amended to “the cryptographical operation[[s]]” for clarity and consistency. Claim 15 is objected to for similar reasons to claim 8. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,197,627. Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear that all of the limitations of claims 1-20 are disclosed by claims 1-17 of U.S. Patent No. 12,197,627.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11,100,254. Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear that all of the limitations of claims 1-20 are disclosed by claims 1-17 of U.S. Patent No. 11,100,254.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 7-9, 11, 12, 14-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaplan et al. (U.S. Pub. No. 2015/0248357 and hereinafter referred to as Kaplan).
As to claim 1, Kaplan discloses a method, comprising:
configuring a processor in a first mode to perform cryptographical operations to recover data in the clear within the processor (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data);
executing, by the processor in the first mode, instructions of a first program (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches executing a program where encryption is not bypassed);
configuring the processor in a second mode to skip the cryptographical operations within the processor (paragraphs [0024] and [0031]-[0033], Kaplan teaches setting the security mode register to bypass an encryption module); and
executing, by the processor in the second mode, instructions of a second program (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches executing a program where encryption is bypassed.).
As to claim 2, Kaplan discloses the method of claim 1, wherein the cryptographical operations include decryption, unscrambling, or inversion, or any combination thereof (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data.).
As to claim 4, Kaplan discloses the method of claim 2, wherein a data item is not in the clear when loaded to the processor from a memory that is external to the processor (paragraphs [0020], [0021], [0024], and [0031]-[0033] and Fig. 1, Kaplan teaches retrieving encrypted data from a separate memory not part of the processor.).
As to claim 5, Kaplan discloses the method of claim 2, wherein the processor is configured in the first mode via setting a first value in a register in the processor; and the processor is configured in the second mode via setting a second value in the register in the processor (paragraphs [0024] and [0031]-[0033] and Fig.1, Kaplan teaches a security mode register in the processor to control encryption/decryption in the processor.).
As to claim 7, Kaplan discloses the method of claim 5, wherein the data is recovered in the clear within a zone in the processor (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data); and when in the first mode, data leaving the zone is protected via encryption, scrambling, or inversion, or any combination thereof (paragraphs [0024], [0031]-[0033] and [0058], Kaplan teaches data leaving from inside the processor may be encrypted depending on the mode.).
As to claim 8, Kaplan discloses a processor, comprising:
a circuit configured to perform cryptographical operation (paragraphs [0024], [0029]-[0030] and Fig. 1, Kaplan teaches an encryption circuit); and
at least one execution unit configured to execute instructions (paragraphs [0024] and [0031]-[0033] and Fig. 1, Kaplan teaches a processor with cores);
wherein the processor is configurable in a first mode to perform the cryptographical operations to recover data in the clear within the processor during execution of instructions of a first program (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data while executing a program); and
wherein the processor is configurable in a second mode to skip the cryptographical operations within the processor during execution of instructions of a second program (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches setting the security mode register to bypass an encryption module while executing a program.).
As to claim 9, Kaplan discloses the processor of claim 8, wherein the cryptographical operations include decryption, unscrambling, or inversion, or any combination thereof (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data.).
As to claim 11, Kaplan discloses the processor of claim 9, wherein a data item is not in the clear when loaded to the processor from a memory that is external to the processor (paragraphs [0020], [0021], [0024], and [0031]-[0033] and Fig. 1, Kaplan teaches retrieving encrypted data from a separate memory not part of the processor.).
As to claim 12, Kaplan discloses the processor of claim 9, further comprising: a register, wherein the processor is configurable in the first mode via setting a first value in the register, and configurable in the second mode via setting a second value in the register (paragraphs [0024] and [0031]-[0033] and Fig.1, Kaplan teaches a security mode register in the processor to control encryption/decryption in the processor.).
As to claim 14, Kaplan discloses the processor of claim 12, wherein the circuit is operable to recover the data in the clear within a zone in the processor (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data); and when in the first mode, protect data leaving the zone via encryption, scrambling, or inversion, or any combination thereof (paragraphs [0024], [0031]-[0033] and [0058], Kaplan teaches data leaving from inside the processor may be encrypted depending on the mode.).
As to claim 15, Kaplan discloses system, comprising:
a memory (paragraphs [0024], [0029]-[0030] and Fig. 1, Kaplan teaches memory); and
a processor (paragraphs [0024], [0029]-[0030] and Fig. 1, Kaplan teaches a processor), including:
a circuit configured to perform cryptographical operation (paragraphs [0024], [0029]-[0030] and Fig. 1, Kaplan teaches an encryption circuit); and
at least one execution unit configured to execute instructions (paragraphs [0024] and [0031]-[0033] and Fig. 1, Kaplan teaches a processor with cores);
wherein the processor is configurable in a first mode to perform the cryptographical operations to recover data in the clear within the processor during execution of instructions of a first program loaded from the memory (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data while executing a program); and
wherein the processor is configurable in a second mode to skip the cryptographical operations within the processor during execution of instructions of a second program loaded from the memory (paragraphs [0024] and [0031]-[0034] and [0037], Kaplan teaches setting the security mode register to bypass an encryption module while executing a program.).
As to claim 16, Kaplan discloses the system of claim 15, wherein the cryptographical operations include decryption, unscrambling, or inversion, or any combination thereof (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data.).
As to claim 18, Kaplan discloses the system of claim 16, wherein a data item is not in the clear when loaded to the processor from the memory that is external to the processor (paragraphs [0020], [0021], [0024], and [0031]-[0033] and Fig. 1, Kaplan teaches retrieving encrypted data from a separate memory not part of the processor.).
As to claim 19, Kaplan discloses the system of claim 16, wherein the processor further comprises: a register, wherein the processor is configurable in the first mode via setting a first value in the register, and configurable in the second mode via setting a second value in the register (paragraphs [0024] and [0031]-[0033] and Fig.1, Kaplan teaches a security mode register in the processor to control encryption/decryption in the processor.).
As to claim 20, Kaplan discloses the system of claim 19, wherein the circuit is operable to recover the data in the clear within a zone in the processor (paragraphs [0024] and [0031]-[0033], Kaplan teaches a security mode register to control encryption/decryption in a processor where one mode performs decryption to obtain data); and when in the first mode, protect data leaving the zone via encryption, scrambling, or inversion, or any combination thereof (paragraphs [0024], [0031]-[0033] and [0058], Kaplan teaches data leaving from inside the processor may be encrypted depending on the mode.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaplan as applied to claims 2, 9 and 16 above, and further in view of Muff et al. (U.S. Pub. No. 2013/0191649 and hereinafter referred to as Muff).
As to claim 3, Kaplan discloses the method of claim 2. Kaplan does not specifically disclose wherein a data item is not in the clear in a cache of the processor as claimed. However, Muff does disclose
wherein a data item is not in the clear in a cache of the processor (paragraphs [0075] and [0109], Muff teaches data is encrypted inside a L1 cache of a processing core.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kaplan with the teachings of Muff for having a data item not be in the clear in a cache because this would improve security.
As to claim 10, Kaplan discloses the processor of claim 9. Kaplan does not specifically disclose further comprising: a cache, wherein a data item is not in the clear in the cache as claimed. However, Muff does disclose
further comprising: a cache, wherein a data item is not in the clear in the cache (paragraphs [0075] and [0109], Muff teaches data is encrypted inside a L1 cache of a processing core.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kaplan with the teachings of Muff for having a data item not be in the clear in a cache because this would improve security.
As to claim 17, Kaplan discloses the system of claim 16. Kaplan does not specifically disclose wherein the processor further comprises: a cache, wherein a data item is not in the clear in the cache as claimed. However, Muff does disclose
wherein the processor further comprises: a cache, wherein a data item is not in the clear in the cache (paragraphs [0075] and [0109], Muff teaches data is encrypted inside a L1 cache of a processing core.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kaplan with the teachings of Muff for having a data item not be in the clear in a cache because this would improve security.
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaplan as applied to claims 5 and 12 above, and further in view of Courtney (U.S. Pub. No. 2019/0362105) Muff et al. (U.S. Pub. No. 2013/0191649 and hereinafter referred to as Muff).
As to claim 6, Kaplan discloses the method of claim 5. Kaplan does not specifically disclose wherein the processor includes a scrambler and an unscrambler configured between a scrambled zone in the processor and an unscrambled zone in the processor as claimed. However, Courtney does disclose
wherein the processor includes a scrambler and an unscrambler in the processor (paragraphs [0024]-[0028], Courtney teaches a scrambling and unscrambling processor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cortney for having a scrambler and an unscrambler because this would improve security.
The combination of teachings between Kaplan and Courtney is not explicitly clear on disclosing the scrambler/unscrambler having different zones as claimed. However, Muff does disclose the different zones (paragraphs [0029], [0104], [0108] and [0109], Muff teaches a protected area to hold encrypted data and another area to hold clear data.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified invention of Kaplan with the teachings of Muff for having the different zones because this would improve security.
As to claim 13, Kaplan discloses the processor of claim 12. Kaplan does not specifically disclose wherein the circuit includes a scrambler and an unscrambler configured between a scrambled zone in the processor and an unscrambled zone in the processor as claimed. However, Courtney does disclose
wherein the circuit includes a scrambler and an unscrambler (paragraphs [0024]-[0028], Courtney teaches a scrambling and unscrambling processor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cortney for having a scrambler and an unscrambler because this would improve security.
The combination of teachings between Kaplan and Courtney is not explicitly clear on disclosing the scrambler/unscrambler having different zones as claimed. However, Muff does disclose the different zones (paragraphs [0029], [0104], [0108] and [0109], Muff teaches a protected area to hold encrypted data and another area to hold clear data.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified invention of Kaplan with the teachings of Muff for having the different zones because this would improve security.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J PLECHA whose telephone number is (571)270-7506. The examiner can normally be reached M-F 8-4:30.
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/THADDEUS J PLECHA/Examiner, Art Unit 2438
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