Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 01/07/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawing
The drawings filed on 01/07/2025 are acceptable.
Claims 1-15 are pending and have been examined.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 01/07/2025, 03/03/2025 and 06/16/2026 are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abdulslam et al. (A Simple Hybrid 3-Level Buck-Boost DC-DC Converter with Efficient PWM Regulation Scheme), hereinafter ‘Abdulslam.
In re to claim 1, Abdulslam disclose a power input circuit (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) comprising: a charge pump (i.e. S1, S2, S3, S4 and Cf); and an LC filter (i.e. L and Cout), wherein the charge pump comprises: a first switch (i.e. S1) configured to receive input power from a power source (i.e. Vin), the input power being input through a first end of the first switch (i.e. Drain of S1); a second switch (i.e. S3) electrically connected to the first switch (i.e. S1), a second end of the first switch being electrically connected to a first end of the second switch (i.e. drain of second switch), and a second end of the second switch (i.e. S3) being electrically connected to the ground (i.e. the ground of fig. 2 (a)); a third switch (i.e. S2) configured to receive the input power from the power source (i.e. Vin), the input power being input through a first end of the third switch (i.e. the drain of S2); a fourth switch (i.e. S4) electrically connected to the third switch (i.e. S3), a second end of the third switch (i.e. source terminal of S3)being electrically connected to a first end of the fourth switch (i.e. the drain of S4), and a second end of the fourth switch being electrically connected to the ground (i.e. the source of S4 is grounded); and a first capacitor (i.e. Cf), a first end of the first capacitor being electrically connected to the second end of the first switch (i.e. Cf connected to Source terminal of S2), and a second end of the first capacitor being electrically connected to the second end of the third switch (i.e. Cf connected to source terminal of S2), wherein the LC filter comprises a first inductor (i.e. L) and a second capacitor (i.e. Cout), and wherein the first inductor (i.e. L) of the LC filter (i.e. L and Cout) is electrically connected to the second end of the first capacitor (i.e. Cf, see fig. 2(a), see col. 1, page 369) .
In re to claim 2, Abdulslam disclose the power input circuit (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 1, wherein the second end of the first capacitor (i.e. Cf) is electrically connected to an input node (i.e. i.e. is the Vx node) of the LC filter (i.e. LCout), wherein the charge pump is configured to output switching power to the input node (i.e. the signal at the Vx nose) of the LC filter (i.e. LCout), based on the input power (i.e. Vin), and wherein the LC filter (i.e. LCout) is configured to receive the switching power via the first inductor (i.e. L), and output an output power through an output node of the LC filter between the first inductor and the second capacitor (i.e. between L and Cout connection node), based on the switching power (i.e. the switching signal Vx, see fig. 2(a) and col. 1, page 369) .
In re to claims 3-5, Abdulslam disclose the power input circuit (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 2, wherein the charge pump (i.e. S1, S2, S3, S4 and Cf); is configured to, based on a first mode (i.e. boost mode), output the switching power having a voltage with a magnitude substantially identical to an input voltage of the input power (i.e. Vin), and wherein the first mode is a combination of the first switch (i.e. S1) being turned off, the second switch (i.e. S3) being turned on, the third switch (i.e. S2) being turned on, and the fourth switch (i.e. S4) being turned off (i.e. see fig. 2(a) and col. 1, page 369); wherein the first capacitor is configured to be charged, based on the first mode (i.e. buck mode), to have a voltage with a magnitude substantially identical to the input voltage of the input power (i.e. see fig. 2(a) and col. 1, page 369); wherein the charge pump (i.e. S1, S2, S3, S4 and Cf); is configured to, based on a second mode (i.e. boost mode), output the switching power having a voltage with a magnitude substantially two times of an input voltage of the input power (i.e. Vin), and wherein the second mode is a combination of the first switch being turned on, the second switch being turned off, the third switch being turned off, and the fourth switch being turned off (i.e. see page 369).
In re to claim 6, Abdulslam disclose the power input circuit (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 2, wherein the charge pump is configured not to output the switching power (i.e. in off mode), based on a third mode, and wherein the third mode is a combination of the first switch being turned off, the second switch being turned off, the third switch being turned off, and the fourth switch being turned on (i.e. switching on/off of switches (i.e. S1, S2, S3 and S4, see fig. 2(a) and page 369).
In re to claims 7-8, Abdulslam disclose the power input circuit (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 2, wherein an output voltage of the output power is determined based on a duty cycle of the first switch, the second switch, the third switch, and/or the fourth switch (i.e. S1, S2, S3 and S4, see fig. 2(a) and page 369); wherein, in order to decrease the output voltage of the output power (i.e. Vout), the duty cycle is adjusted to be shortened, and wherein, in order to increase the output voltage of the output power, the duty cycle is adjusted to be extended (i.e. see pages 369-370).
In re to claims 10-11, Abdulslam disclose an electronic device (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) comprising: a power input circuit (i.e. S1, S2, S3, S4 and Cf,) of claim 1; a power source (i.e. Vin); and a processor; wherein the processor is configured to control the charge pump (i.e. S1, S2, S3, S4 and Cf) in a first mode, a second mode and/or a third mode (i.e. it is implicit that the converter can not operate without a processor/controller, thus Abdulslam discloses the processor/controller).
In re to claims 12-13, Abdulslam disclose an electronic device (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 11, wherein the processor is configured to: identify a necessary voltage of the output power (i.e. Vout); and control a duty cycle of the first switch, the second switch , the third switch , and/or the fourth switch (i.e. S1, S2, S3 and S4), based on the necessary voltage; wherein the processor is configured to: adjust the duty cycle to be shortened, based on the necessary voltage of the output power being smaller than an existing output voltage (i.e. Vout) of the output power; and adjust the duty cycle to be extended, based on the necessary voltage of the output power being greater than the existing output voltage of the output power (i.e. it is implicit that the converter cannot operate without a processor/controller, thus Abdulslam discloses the processor/controller).
In re to claim 15, Abdulslam disclose an electronic device (i.e. S1, S2, S3, S4, Cf, L and Cout fig. 2 (a)) of claim 11, wherein the processor is configured to control the charge pump to switch between the first mode and the third mode such that an output voltage of the output power is included in a range equal to or smaller than an input voltage of the input power (i.e. it is implicit that the converter cannot operate without a processor/controller, thus Abdulslam discloses the processor/controller).
Allowable Subject Matter
Claims 9 and 14 are objected to as being dependent upon a rejected base claim but
would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claim 9, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein an output voltage of the output power is determined within a range equal to or smaller than a voltage with a magnitude substantially two times of an input voltage of the input power and equal to or greater than the input voltage, as the charge pump switches between the first mode and the second mode; and/or wherein the output voltage of the output power is determined within a range equal to or smaller than an input voltage of the input power, as the charge pump switches between the first mode and the third mode”.
In re to claim 14, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the processor is configured to control the charge pump to switch between the first mode and the second mode such that an output voltage of the output power is included in a range equal to or smaller than a voltage with a magnitude substantially two times of an input voltage of the input power and equal to or greater than the input voltage.”
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838
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