DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/28/26 has been entered.
Response to Amendment
This final Office action is in response to the amendment filed 8/28/26 which amended claims 1, 2, 8, 9, 15, and 16. The amendments return the claims to their original limitations and all other claims remain in their original condition, so the double patenting rejection made originally is repeated herein and made final.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,222,869. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has essentially just rearranged and reworded the claims, which is an obvious modification of patented claims. The following chart shows two exemplary claims side by side, one from the instant application and one from the patent:
Instant claim 20 (and its preceding claims, with some sections rearranged to more clearly show correspondence)
Patented claim 20 (and its preceding claim)
15. A processor, comprising: a plurality of execution units configured to execute instructions, wherein instructions to be executed in the processor are grouped into a plurality of groups of instructions, and wherein the plurality of groups of instructions are classified into a plurality of domains for execution in the processor;
19. An apparatus, comprising: a memory configured to store a plurality of routines classified in a plurality of domains;
a processor coupled with the memory;
and a memory management unit configured to compute physical memory addresses from virtual memory addresses used by instructions being executed in the processor;
20. The processor of claim 19, wherein the table entry includes a plurality of permission settings for the plurality of domains respectively and a base for computing the physical memory address from the virtual memory address.
and a memory management unit, comprising: a page table having a plurality of page table entries, including a first page table entry configured to specify: a base to map a virtual memory address region to a physical memory address region in the memory;
wherein the processor is configured to, during execution of an instruction in the processor to access a memory region among a plurality of memory regions: determine a domain, among the plurality of domains, for the execution of the instruction in the processor based on the instruction being included in one of the plurality of groups; and determine, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
19. The processor of claim 18, wherein the permission setting is configured in a table entry used to compute a physical memory address in the memory region from a virtual memory address used in the execution of the instruction.
16. The processor of claim 15, further configured to: determine a type, among a plurality of types, of accessing the memory region during the execution of the instruction; wherein the permission setting is pre-associated with the type.
and a list of permissions for the plurality of domains respectively; and a logic circuit configured to, in response to an instruction of a routine executed in a processor to access a virtual memory address in the virtual memory address region: determine, based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region; and control, based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region.
18. The processor of claim 17, wherein the plurality of domains include: instructions of hypervisor; instructions of operating system; and instructions of application.
20. The apparatus of claim 19, wherein the plurality of domains comprises a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof; wherein the first page table entry specifies, for each respective type of memory access among a plurality of types of memory access and for each of the plurality of domains, a permit;
17. The processor of claim 16, wherein the plurality of types include read, write, and execution.
and wherein the plurality of types of memory access include a type of memory access corresponding to operations of reading the memory, a type of memory access corresponding to operations of writing to the memory, or a type of memory access corresponding to operations of loading one or more instructions from the memory for execution, or any combination thereof.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,436,156. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has essentially just rearranged and reworded the claims, which is an obvious modification of patented claims. The following chart shows two exemplary claims side by side, one from the instant application and one from the patent:
Instant claim 17 (and its preceding claims)
Patented claim 20 (and its preceding claim)
15. A processor, comprising: a plurality of execution units configured to execute instructions, wherein instructions to be executed in the processor are grouped into a plurality of groups of instructions, and wherein the plurality of groups of instructions are classified into a plurality of domains for execution in the processor; and a memory management unit configured to compute physical memory addresses from virtual memory addresses used by instructions being executed in the processor; wherein the processor is configured to, during execution of an instruction in the processor to access a memory region among a plurality of memory regions: determine a domain, among the plurality of domains, for the execution of the instruction in the processor based on the instruction being included in one of the plurality of groups;
19. An apparatus, comprising: a memory; a processor coupled with the memory; and wherein the processor is configured to map a virtual memory address to a physical memory address using a page table entry during an execution of an instruction of a routine that is in a first domain; wherein the page table entry has a permission bit for a type of memory access for each domain in a predefined set of domains of routines;
and determine, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
16. The processor of claim 15, further configured to: determine a type, among a plurality of types, of accessing the memory region during the execution of the instruction; wherein the permission setting is pre-associated with the type.
and wherein the processor is further configured to control, in accordance with a respective permission bit for the first domain, a memory access of the type in response to the instruction of the routine causing the processor to use the virtual memory address to access the physical memory address.
17. The processor of claim 16, wherein the plurality of types include read, write, and execution.
20. The apparatus of claim 19, wherein the type of memory access is: read from the memory; write to the memory; or execute an instruction stored in the memory.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10,915,457. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has essentially just rearranged and reworded the claims, which is an obvious modification of patented claims. The following chart shows two exemplary claims side by side, one from the instant application and one from the patent:
Instant claim 20 (and its preceding claims, with some sections rearranged to more clearly show correspondence)
Patented claim 20 (and its preceding claims)
15. A processor, comprising: a plurality of execution units configured to execute instructions, wherein instructions to be executed in the processor are grouped into a plurality of groups of instructions, and wherein the plurality of groups of instructions are classified into a plurality of domains for execution in the processor;
18. A computing device, comprising: at least one register; at least one execution unit;
and a memory management unit configured to compute physical memory addresses from virtual memory addresses used by instructions being executed in the processor; wherein the processor is configured to, during execution of an instruction in the processor to access a memory region among a plurality of memory regions: determine a domain, among the plurality of domains, for the execution of the instruction in the processor based on the instruction being included in one of the plurality of groups; and determine, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
16. The processor of claim 15, further configured to: determine a type, among a plurality of types, of accessing the memory region during the execution of the instruction; wherein the permission setting is pre-associated with the type.
and a memory management unit configured to manage a page table entry containing permission bits corresponding to predefined types of memory accesses made by executions of routines in predefined domains;
19. The processor of claim 18, wherein the permission setting is configured in a table entry used to compute a physical memory address in the memory region from a virtual memory address used in the execution of the instruction.
wherein, in response to a routine executed in the computing device accessing a virtual memory address, the memory management unit is configured to generate a physical memory address using the page table entry;
20. The processor of claim 19, wherein the table entry includes a plurality of permission settings for the plurality of domains respectively and a base for computing the physical memory address from the virtual memory address.
and the computing device is configured to determine whether to reject the routing accessing the virtual memory address based on a permission bit corresponding to an execution domain of the routine and a type of memory access made using the virtual memory address.
17. The processor of claim 16, wherein the plurality of types include read, write, and execution.
19. The computing device of claim 18, wherein the predefined types of memory accesses comprise read data from virtual addresses, write data to virtual addresses, or execute instructions stored at virtual addresses, or any combination thereof.
18. The processor of claim 17, wherein the plurality of domains include: instructions of hypervisor; instructions of operating system; and instructions of application.
20. The computing device of claim 19, wherein the predefined domains comprise at least one of a domain of hypervisor, a domain of operating system, or a domain of application, or any combination thereof.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132
Prosecution Insights